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參數(shù)資料
| 型號： | VG4632321AQ-7 |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
| 中文描述： | 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 16/81頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | VG4632321AQ-7 |
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Document:
Rev.1
Page 16
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page. But, lnterleave Mode only supports
burst length of 4 and 8.
A3
Addressing Mode
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n+m), in the
table is larger than 255, only the least significant 8 bits are effective.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the
address bits in the sequence shown in following table.
CAS Latency Field (A6 ~ A4)
This field specifies the number of clock cycles from the assertion of the Read command
to the first read data. The minimum value of CAS Latency depends on the frequency of
CLK. And this value satisfying the following formula must be programmed into this field.
≤
t
CAC (min)
CAS Latency x t
CK
A5
0
0
1
1
X
0
Sequential
1
Interleave
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
Burst Length
Data n
Column Address
Burst Length
Data 0
A7 A6 A5 A4 A3 A2 A1 A0
Data 1
A7 A6 A5 A4 A3 A2 A1 A0
Data 2
A7 A6 A5 A4 A3 A2 A1 A0
Data 3
A7 A6 A5 A4 A3 A2 A1 A0
Data 4
A7 A6 A5 A4 A3 A2 A1 A0
Data 5
A7 A6 A5 A4 A3 A2 A1 A0
Data 6
A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A7 A6 A5 A4 A3 A2 A1 A0
A6
0
0
0
0
1
A4
0
1
0
1
X
CAS Latency
Reserved
1 clock
2 clocks
3 clocks
Reserved
2 words:
4 words
:
8 words:
Full Page: Column address is repeated until terminated.
4 Words
8 Words
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| VG4632321AQ-7R | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
| VG4632321AQ-45 | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
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| VG4632321A | CHASSIS PLATE; IP rating:IP67; Temp, op. max:100(degree C); Temp, op. min:-40(degree C) RoHS Compliant: Yes |
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| VG4632321AQ-7R | 制造商:VML 制造商全稱:VML 功能描述:524,288x32x2-Bit CMOS Synchronous Graphic RAM |
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