參數(shù)資料
型號: VG4632321AQ-7
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 524,288x32x2-Bit CMOS Synchronous Graphic RAM
中文描述: 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 21/81頁
文件大小: 1965K
代理商: VG4632321AQ-7
Document:
Rev.1
Page 21
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Recommended D.C. Operating Conditions (V
DD
= 3.3V 0.3V, Ta = 0 ~ 70°C)
Description/test condition
Symbol
-4.5
-5
-5.5
-6
-7
Unit
Note
Min. Max. Min. Max. Min. Max Min. Max. Min. Max.
230
220
Operating Current
tRC
, Outputs Open
)
Address changed once during t
CK(min)
.
Burst Length = 1, One bank active
I
DD1
210
200
180
mA
3,4
Precharge Standby Current in non power-down
mode
t
CK
= 15ns,
Input signals are changed once during 30ns.
(min)
,
(min)
I
DD2N
45
45
45
45
45
3
Precharge Standby Current in non power-down
mode
CKE
V
IH
t
CK
=
Input signals are stable
,
(min)
,
(max)
I
DD2NS
20
20
20
20
20
Precharge Standby Current in power-down
mode
t
CK
=15ns,
CKE
V
IL
(max)
I
DD2P
2
2
2
2
2
3
Precharge Standby Current in power-down
mode
CKE
V
IL
t
CK
=
,
(max)
,
(max)
I
DD2PS
2
2
2
2
2
Active Standby Current in non power down
mode
(min)
, t
CK
= 15ns(Both Bank Active)
Input signals are changed once during 30ns.
I
DD3N
50
50
50
50
50
3
Active Standby Current in power-down mode
(max)
, t
CK =
15ns,
CS
V
IH(min)
(Both Bank Active)
Operating Current (Page Burst, and All Bank
activated)
t
CCD
= t
CCD(min)
, Outputs Open,
Multi-bank interleave, gapless data
I
DD3P
5
5
5
5
5
I
DD4
310
290
275
260
230
4,5
Refresh Current
t
RC
t
RC
(min)
(t
REF
= 32ms)
I
DD5
230
220
210
200
180
3
Self Refresh Current
CKE
0.2V
I
DD6
3.5
3.5
3.5
3.5
3.5
Operating Current (One Bank Block Write)
t
CK
= t
CK(min)
, Outputs Open, t
BWC
= t
BWC(min)
I
DD7
230
210
200
180
150
Parameter
Description
Min.
Max.
Unit
μ
Note
I
IL
Input Leakage Current
All other pins not under test = 0V)
(
-5
5
A
I
OL
Output Leakage Current
Output disable, (
)
-5
5
A
V
OH
LVTTL Output ”H” Level Voltage
(l
OUT
= -2mA)
2.4
-
V
tRC min
(
CS
V
IH
CKE
V
IH
CLK
V
IL
CLK
V
IL
CKE
V
IH
CKE
V
IL
0V
VIN
VDD
0V
VOUT
VDDQ
μ
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