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參數(shù)資料
| 型號： | VG4632321AQ-7 |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
| 中文描述： | 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 10/81頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | VG4632321AQ-7 |
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Document:
Rev.1
Page 10
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Q
DSF
BankActivate
command
MR7
MR6
MR5
MR4
MR3
MR1
MR0
MR2
CK
D
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CELL
DRAM
0 = Masked
1 = Not Masked
Note:
Only lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without auto precharge function may be interrupted by a subsequent Write/Block
Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt
comes from Write/Block Write command can occur on any clock cycle following the previous Write
command ( refer to the following figure).
DQM0
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DIN B
2
Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)
DIN B
3
1 Clk Interval
DIN A
0
DIN B
0
DIN B
1
DQ’s
The Read command that interrupts a write burst without auto precharge function should
be issued one cycle after the clock edge at which the last data-in element is registered. In
order to avoid data contention, input data must be removed from the DQs at least one clock
cycle before the first read data appears on the outputs (refer to the following figure). Once the
Read command is registered, the data inputs will be ignored, and writes will not be executed.
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