參數(shù)資料
型號(hào)： VG4632321AQ-7
廠商： VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 524,288x32x2-Bit CMOS Synchronous Graphic RAM
中文描述： 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 7/81頁(yè)
文件大?。?/td> 1965K
代理商： VG4632321AQ-7
Document:
Rev.1
Page 7
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
The Read command is used to read burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least t
RCD
(min.) before Read command is issued.
During read bursts, the valid data-out element from the starting column address will be available
following the CAS latency after the issue of Read command. Each subsequent data-out element will
be valid by the next positive clock edge (refer to the following figure). The DQs goes into
high-impedance at the end of the burst, unless other command was initiated. The burst length, burst
sequence, and CAS latency are determined by the mode register which is already prgrammed.A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and con-
tinue).
CLK
COMMAND
READ A
T0
T1
T2
T3
CAS Iatency = 1
t
CK1
,DQ’s
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
Burst Read Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
The read data appears on the DQs subjects to the values on the DQM inputs two clocks early (i.e.
DQM latency is two clocks for output buffers). A read burst without auto precharge function may be
interrupted by a subsequent Read or Write/Block Write command to the same bank or the other
active bank before the end of burst length. It may be interrupted by a BankPrecharge/PrechargeAll
command to the same bank too. The interrupt comes from Read command can occur on any clock
cycle following a previous Read command (refer to the following figure).
CAS Iatency = 2
t
CK2
,DQ’s
CAS Iatency = 3
t
CK3
,DQ’s
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
CAS Iatency = 1
t
CK1
,DQ’s
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
DOUT A
0
DOUT B
0
DOUT B
1
DOUT B
2
Read Interrupted by a Read (Burst Length = 4, CAS Latency = 1, 2, 3)
CAS Iatency = 2
t
CK2
,DQ’s
CAS Iatency = 3
t
CK3
,DQ’s
DOUT B
3
DOUT B
3
DOUT B
3
The DQM inputs are used to avoid I/O contention on DQ pins when the interrupt comes from
Write/Block Write command. The DQMs must be asserted (High) at least two clocks prior to the
Write/Block Write command to suppress data-out on DQ pins. To guarantee DQ pins against the I/O
contention, a single cycle with high-impedance on DQ pins must occur between the last read data
and the Write/Block Write command (refer to the following three figures). If the data output of burst
read occurs at the second clock of burst write, the DQMs must be asserted (High) at least one clock
prior to the Write/Block Write command to avoid internal bus contention.
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