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參數(shù)資料
| 型號(hào)： | VG4632321AQ-7 |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
| 中文描述： | 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 24/81頁(yè) |
| 文件大?。?/td> | 1965K |
| 代理商： | VG4632321AQ-7 |
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Document:
Rev.1
Page 24
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
2. All voltages are referenced to V
SS
.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum
value of t
CK
and t
RC
. Input signals are changed one time during t
CK
. Assume that there is only one read/write cycle
during t
RC
(min).
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Assume minimum column address update cycle t
CCD
(min).
6. Power-up sequence is described in Note 11.
7. A.C. Test Conditions
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels
3.0V / 0.0V
Transition Time (Rise and Fall) of Input Signals
1ns
Reference Level of Input Signals
1.4V
3.3V
1.2K
870
30pF
Output
LVTTL D.C. Test Load (A)
1.4V
50
30pF
Output
ZO=50
LVTTL A.C. Test Load (B)
8. Transition times are measured between V
IH
and V
IL
. Transition (rise and fall) of input signals are fixed slope (1 ns).
9. t
HZ
defines the time at which the outputs achieve the open circuit condition and are not reference levels.
10. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycles = specified value of timing/Clock cycle time (count fractions as a whole number)
Latency relationship to frequency (Unit : clock cycles)
-4.5 Version (Calculation with t
CK
= 4.5ns ~ 30ns)
Clock period
(t
CK
)
55ns
30ns
20ns
15ns
10ns
4.5ns
t
RC
t
RP
15ns
1
1
1
2
4
t
RRD
9ns
1
1
1
1
2
t
RAS
40ns
2
2
3
4
9
t
RSC
9ns
1
1
1
1
2
t
RCD
15ns
1
1
1
2
4
2
3
4
6
13
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|---|---|
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