參數(shù)資料
型號(hào): VG4632321AQ-7
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 524,288x32x2-Bit CMOS Synchronous Graphic RAM
中文描述: 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 23/81頁
文件大小: 1965K
代理商: VG4632321AQ-7
Document:
Rev.1
Page 23
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 3.3V
0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.
±
symbol
A.C. Parameter
-4.5
-5
-5.5
-6
-7
unit
note
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
RC
t
RCD
t
RP
Row cycle time
55
55
56.5
60
62
ns
10
RAS to CAS delay
15
15
16.5
18
20
10
Precharge to refresh/row activate
command
15
15
16.5
18
20
10
t
RRD
t
RAS
t
WR
t
CK1
t
CK2
t
CK3
t
CH
t
CL
t
AC1
t
AC2
t
AC3
t
T
t
CCD
t
OH
t
LZ
t
HZ1
t
HZ2
t
HZ3
t
IS
t
IH
t
SRX
t
PDE
t
RSC
t
BWC
t
DAL2
Row activate to row activate delay
9
10
11
12
14
10
Row activate to precharge time
40
100K
40
100K
40
100K
42
100K
42
100K
Write recovery time
7
7
7
7
7
Clock cycle time
CL* = 1
-
-
-
18
18
CL* = 2
-
-
-
8
9
CL* = 3
4.5
5
5.5
6
7
Clock high time
2
2
2
2
2.5
Clock low time
2
2
2
2
2.5
Access time from CLK
(positive edge)
CL* = 1
-
-
-
17
17
CL* = 2
-
-
-
6
6
CL* = 3
4
4.5
5
5.5
6
Transition time of CLK (Rise and Fall)
0.5
10
0.5
10
0.5
10
0.5
10
0.5
10
CAS to CAS Delay time
1
1
1
1
1
CLK
Data output hold time
1.5
2
2
2
2
ns
Data output low impedance
2
2
2
2
2
Data output high impedance(CL = 1)
-
-
-
-
-
-
2
5
3
6
9
Data output high impedance(CL = 2)
-
-
-
-
-
-
2
5
3
6
9
Data output high impedance(CL = 3)
2
4
2
4.5
2
4.5
2
5
3
5
9
Data/Address/Control Input setup time
1.5
1.5
1.5
1.5
2
Data/Address/Control Input hold time
0.8
0.8
1
1
1
Minimum CKE ”High”for Self-Refresh exit
1
1
1
1
1
CLK
Power Down Exit set-up time
4
4
4
5
5
ns
(Special) Mode Register Set Cycle time
2
2
2
2
2
CLK
10
Block Write Cycle time
1
1
1
1
1
CLK
Data-in to ACT (REF) Command (CL = 2)
-
-
-
1clk+
t
RP
1clk+
t
RP
1
1clk+
t
RP
1clk+
t
RP
1
ns
t
DAL3
Data-in to ACT (REF) Command (CL = 3) 1clk+
t
RP
1
1clk+
t
RP
1
1clk+
t
RP
1
t
BPL
t
REF
Block Write to Precharge command
CLK
Refresh time
32
32
32
32
32
ms
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