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| 型號： | VG4632321AQ-7 |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 524,288x32x2-Bit CMOS Synchronous Graphic RAM |
| 中文描述： | 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 25/81頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | VG4632321AQ-7 |
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Document:
Rev.1
Page 25
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
-5 Version (Calculation with t
CK
= 5ns ~ 30ns)
Clock period
(t
CK
)
30ns
20ns
15ns
10ns
5ns
-5.5 Version (Calculation with t
CK
= 5.5ns ~ 30ns)
Clock period
(t
CK
)
56.5ns
30ns
20ns
15ns
10ns
5.5ns
-6 Version (Calculation with t
CK
= 6ns ~ 30ns)
Clock period
(t
CK
)
30ns
20ns
15ns
10ns
6ns
-7 Version (Calculation with t
CK
= 7ns ~ 30ns)
Clock period
(t
CK
)
30ns
20ns
15ns
10ns
7ns
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to V
DD
and V
DDQ
(simultaneously) when all input signals are held “NOP”
state and CKE = ”H”, DQM = ”H”. The CLK signal must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held “high” (V
DD
levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
t
RC
55ns
2
3
4
6
11
t
RP
15ns
1
1
1
2
3
t
RRD
10ns
1
1
1
1
2
t
RAS
40ns
2
2
3
4
8
t
RSC
10ns
1
1
1
1
2
t
RCD
15ns
1
1
1
2
3
t
RC
t
RP
t
RRD
11ns
1
1
1
2
2
t
RAS
40ns
2
2
3
4
8
t
RSC
11ns
1
1
1
2
2
t
RCD
16.5ns
1
1
2
2
3
16.5ns
1
1
2
2
3
2
3
4
6
11
t
RC
60ns
2
3
4
6
10
t
RP
18ns
1
1
2
2
3
t
RRD
12ns
1
1
1
2
2
t
RAS
42ns
2
3
3
5
7
t
RSC
12ns
1
1
1
2
2
t
RCD
18ns
1
1
2
2
3
t
RC
62ns
3
4
5
7
10
t
RP
20ns
1
1
2
2
3
t
RRD
14ns
1
1
1
2
2
t
RAS
42ns
2
3
3
5
6
t
RSC
14ns
1
1
1
2
2
t
RCD
20ns
1
1
2
2
3
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