參數(shù)資料
型號： UPD70433R-12
廠商： NEC Corp.
元件分類： 16位微控制器
英文描述： V55PITM 16-BIT MICROPROCESSOR
中文描述： V55PITM 16位微處理器
文件頁數(shù)： 49/166頁
文件大小： 772K
代理商： UPD70433R-12
49
μ
PD70433
Table 6-1. Transfer Modes
DMA Start Source
Transfer
Mode
On–Chip
Software
Peripheral
Trigger
Single
transfer
mode
Available
Available
Available
Stops when the DMARQ pin is
driven low during the transfer.
Reset of EDMA bit of DMAMn
register
Not acknowledged
during transfer.
Acknowledged at
other times.
Single
step
mode
Available
*
Available
Available
Burst
mode
None (stop disabled during the
transfer)
*
The DMA start source is an on-chip timer interrupt, and transfer is possible only when the transfer I/O specification is
external.
Table 6-2. Correspondence Between Operating Modes and Transfer Modes
Possible Transfer Modes*
Operating Mode
Transfer Type
<1>
<2>
<3>
<4>
Intelligent DMA mode–1
(ring buffer method)
I/O (SFR)
→
Memory
Yes
Yes
No
No
Intelligent DMA mode–2
(counter control method)
Memory
→
I/O (SFR)
No
No
Yes
Yes
Next address specification mode
I/O (SFR)
←→
Memory
Yes
Yes
No
No
(Stop at end)
I/O
←→
Memory
Yes
Yes
Yes
Yes
(Repetition)
I/O
←→
Memory
Yes
Yes
Yes
No
(Stop at end)
Memory
←→
Memory
Yes
No
Yes
Yes
(Repetition)
Memory
←→
Memory
Yes
No
Yes
No
*
Transfer modes
<1> Single transfer mode
<2> Demand release mode
<3> Single step mode
<4> Burst mode
Not Available
Not Available
Available
Available
*
Available
Available
2–channel
operating mode
Memory–memory
transfer mode
Demand
release
mode
Reset of EDMA bit of DMAMn
register
Reset of EDMA bit of DMAMn
Acknowledged
register
Not acknowledged
Acknowledged
STOP Method
Interrupt
DMARQ Pin
相關(guān)PDF資料
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