
μ
P
1
Operation Code
Flags
Mnemonic
Operand(s)
Bytes
Operation
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
AC CY V
P
S
Z
(SP – 1, SP – 2)
←
PSW, (SP – 3, SP – 4)
←
PS
(SP – 5, SP – 6)
←
PC, SP
←
SP – 6
IE
←
0, BRK
←
0
PS
←
(15, 14), PC
←
(13, 12)
3
1 1 0 0 1 1 0 0
1
BRK
(SP – 1, SP – 2)
←
PSW, (SP – 3, SP – 4)
←
PS
(SP – 5, SP – 6)
←
PC, SP
←
SP – 6
IE
←
0, BRK
←
0
PS
←
(n
×
4 + 3, n
×
4 + 2), PC
←
(n
×
4 + 1, n
×
4) n = imm8
imm8
(
≠
3)
1 1 0 0 1 1 0 1
2
If V = 1:
(SP – 1, SP – 2)
←
PSW, (SP – 3, SP – 4)
←
PS
(SP – 5, SP – 6)
←
PC, SP
←
SP – 6
IE
←
0, BRK
←
0
PS
←
(19, 18), PC
←
(17, 16)
BRKV
1 1 0 0 1 1 1 0
1
RETI
1 1 0 0 1 1 1 1
1
PC
←
(SP + 1, SP), PS
←
(SP + 3, SP + 2)
PSW
←
(SP + 5, SP + 4), SP
←
SP + 6
R
R
R
R
R
R
RETRBI
*
0 0 0 0 1 1 1 1
1 0 0 1 0 0 0 1
2
PC
←
Value of PC save area in currently selected bank
register, PSW
←
Value of PSW save area in currently
selected bank register
R
R
R
R
R
R
FINT
*
0 0 0 0 1 1 1 1
1 0 0 1 0 0 1 0
2
Indicates to interrupt controller incorporated in CPU
that interrupt servicing has ended.
If (mem32) > reg16 or (mem32 + 2) < reg16
(SP – 1, SP – 2)
←
PSW, (SP – 3, SP – 4)
←
PS
(SP – 5, SP – 6)
←
PC, SP
←
SP – 6
IE
←
0, BRK
←
0
PS
←
(23, 22), PC
←
(21, 20)
CHKIND
reg, mem32
0 1 1 0 0 0 1 0
mod reg mem
2 to 4
0 0 0 0 1 1 1 1
0 0 1 0 1 1 0 1
BRKCS
*
reg16
3
1 1 0 0 0
reg
0 0 0 0 1 1 1 1
1 0 0 1 0 1 0 0
PSW save area in currently selected register bank
←
PSW
PC save area in currently selected register bank
←
PC
RB3-0
←
reg16 low-order 4 bits
PSW
←
Value of PSW save area in newly selected register bank
PC
←
Value of PC save area in newly selected register bank
TSKSW
*
reg16
3
×
×
×
×
×
×
1 1 1 1 1
reg
If CH + CL
≥
16: BW, DW
→
DS1:IY output to transmit
buffer If CH + CL < 16: CH + CL
→
CH, BW, DW
→
BW
Part exceeding 16 bits: CH+CL–16
→
CH, BW, DW
→
BW
ALBIT
0 0 0 0 1 1 1 1
1 0 0 1 1 0 1 0
2
U
×
U
U
U
×
Stores 1 line pixel data change point information in
change point table (start white run length).
COLTRP
0 0 0 0 1 1 1 1
1 0 0 1 1 0 1 1
2
MHENC
0 0 0 0 1 1 1 1
1 0 0 1 0 0 1 1
2
Generates MH code from change point table.
U
×
U
U
U
×
MRENC
0 0 0 0 1 1 1 1
1 0 0 1 0 1 1 1
2
Generates MR code from change point table.
U
×
U
U
U
×
I
G
I
temp
←
PSW
RB3 to 0
←
reg16 low–order 4 bits, IE
←
0, BRK
←
0
PSW save area in newly selected register bank
←
temp
PC save area in newly selected register bank
←
PC
*
This instruction is newly added to the V20 or V30.
D
R
s