
134
μ
PD70433
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
HLDAK
↑
delay time from HLDRQ
↓
60
t
DHQHA
0.5T – 15
3.5T + 35
ns
Bus output delay time from HLDRQ
↓
61
t
DHQC
0.5T + 45
ns
HLDRQ low-level width
62
t
WHQL
2T
ns
HLDAK low-level width
63
t
WHAL
3T – 10
ns
BUSLOCK delay time from CLKOUT
↑
64
t
DKBL
0
27
ns
DMARQm setup time (to CLKOUT
↓
)
65
t
SDQK
Except demand release
mode; m = 0, 1
25
ns
DMARQm high-level width
66
t
WDQH
Except demand release
mode; m = 0, 1
2T
ns
DMARQm low-level width
67
t
WDQL
Except demand release
mode; m = 0, 1
2T
ns
DMARQm setup time (to CLKOUT
↑
)
68
t
SKDQ
Demand release mode;
m = 0 or 1
5
ns
DMARQm low-level hold time
(from CLKOUT
↓
)
69
t
HKDQ
Demand release mode;
m = 0 or 1
12
ns
DMAAKm
↓
delay time from CLKOUT
↑
70
t
DKDA
m = 0 or 1
0
27
ns
DMAAKm low-level width
71
t
WDAL
m = 0 or 1
(3 + n + N)T – 10
ns
TCEm
↓
delay time from CLKOUT
↑
72
t
DKTE
m = 0 or 1
0
27
ns
TCEm low-level width
73
t
WTCL
m = 0 or 1
T – 10
ns
TOUT high-level width
74
t
WTOH
8T – 10
ns
TOUT low-level width
75
t
WTOL
8T – 10
ns
WDTOUT low-level width
76
t
WWTL
32T – 10
ns
Input
8T
ns
SCK cycle time
77
t
CYSK
Output
8T – 10
ns
Input
4T – 10
ns
SCK high-level width
78
t
WSKH
Output
4T – 10
ns
Input
4T – 10
ns
SCK low-level width
79
t
WSKL
Output
4T – 10
ns
SI, SB setup time (to SCK
↑
)
80
t
SSSK
50
ns
SI, SB hold time (from SCK
↑
)
81
t
HSKS
150
ns
82
t
DSKSB1
IOE mode (CMOS push-pull
output)
0
90
ns
SO, SB delay time from SCK
↓
83
t
DSKSB2
SBI mode (open-drain
output, RL = 1 k
)
0
190
ns
SB high-level hold time (from SCK
↑
)
84
t
HSKSB
4T
ns
SBI mode
SB low-level setup time (to SCK
↓
)
85
t
SSBSK
4T
ns
SB high-level width
86
t
WSBH
4T
ns
SB low-level width
87
t
WSBL
4T
ns
n :
N :
T :
Number of address wait states
Number of data wait states
t
CYK
Remark
Numbers in the Symbol column correspond to numbers in the timing charts.