參數(shù)資料
型號： UPD70433R-12
廠商： NEC Corp.
元件分類： 16位微控制器
英文描述： V55PITM 16-BIT MICROPROCESSOR
中文描述： V55PITM 16位微處理器
文件頁數(shù)： 48/166頁
文件大小： 772K
代理商： UPD70433R-12
48
μ
PD70433
6.
DMA FUNCTION (DMA CONTROLLER)
The V55PI incorporates a 2-channel DMA controller which controls execution of memory-to-I/O or memory-to-memory
DMA transfers on the basis of DMA requests generated by an on-chip peripheral hardware (serial interface, parallel interface,
or timer), the external DMARQ pin or a software trigger.
Each channel of the DMA controller further comprises a main channel and a sub-channel: the operating mode determines
whether the main channel and sub-channel are used as a single channel or as separate channels. When used as separate
channels, function for a maximum of 4 channels can be constructed.
6.1
FEATURES
Two independent DMA channels (max. 4-channel configuration possible)
Four transfer modes
Single transfer mode
... One DMA transfer cycle is executed in response to one DMA request.
Demand release mode... Consecutive DMA transfer cycles are executed while DMA request is active.
Single-step mode
... DMA transfer cycles and CPU bus cycles are executed alternately after DMA
request generation.
Burst mode
... For each DMA request, the specified number of DMA transfer cycles are executed
consecutively.
Five operating modes
Intelligent DMA mode–1 (ring buffer system)
... DMA transfers to ring buffer are controlled.
Intelligent DMA mode–2 (counter control system) ... Transfer data is transferred consecutively, divided into
an arbitrary number of bytes.
Next address specification mode
... Consecutive transfers are possible between different
transfer buffers.
2-channel operating mode
... Main channel and subchannel are used as independent
channels.
Memory-to-memory transfer mode
... Two bus cycles are started for one DMA transfer cycle,
and memory-to-memory transfer is executed.
3 clocks/1 bus cycle (no wait case)
Transfer objects
External I/O
←→
memory
... 1 DMA transfer cycle/1 bus cycle
SFR (internal I/O)
←→
memory
... 1 DMA transfer cycle/1 bus cycle
Memory
←→
memory (memory includes SFR) ... 1 DMA transfer cycle/2 bus cycles
Byte transfer/word transfer selectable
Transfer address increment/decrement/non-update selectable
DMA transfer end signal (TCE0, TCE1) output
24-bit DMA memory address registers (MAR0, MAR1)
21-bit terminal counters (TC0, TC1)
External DMA request signal input pins (DMARQ0, DMARQ1: alternate function as port P80 and P81 pins)
External DMA acknowledge signal output pins (DMAAK0, DMAAK1)
相關(guān)PDF資料
PDF描述
UPD70433R-16 V55PITM 16-BIT MICROPROCESSOR
UPD70433GD-12-5BB V55PITM 16-BIT MICROPROCESSOR
UPD70433GD-16-5BB V55PITM 16-BIT MICROPROCESSOR
UPD70433GJ-12-3EB V55PITM 16-BIT MICROPROCESSOR
UPD70433GJ-16-3EB V55PITM 16-BIT MICROPROCESSOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD70433R-16 制造商:NEC 制造商全稱:NEC 功能描述:V55PITM 16-BIT MICROPROCESSOR
UPD705100 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER
UPD705100GJ-100-8 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER
UPD705100GJ-100-8EU 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER
UPD705101 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT MICROPROCESSOR
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