
137
μ
PD70433
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
ASTB
↑
delay time from RD
↑
, IORD
↑
119
t
DRSTH
0
ns
RD
↑
, IORD
↑
delay time from WRL
↑
, WRH
↑
, IOWR
↑
120
t
DWRH
0
ns
DEX delay time from CLKOUT
↓
31
t
DKDX
0
27
ns
DEX hold time (from CLKOUT
↓
)
32
t
HKDX
0
ns
Data input setup time (to CLKOUT
↓
)
33
t
SDK
11
ns
Data input hold time (from CLKOUT
↓
)
34
t
HKDR
0
ns
WR
↓
delay time from CLKOUT
↓
35
t
DKWL
0
22
ns
WR
↑
delay time from CLKOUT
↓
36
t
DKWH
0
22
ns
WR low-level width
37
t
WWL
(N + 1)T – 12
ns
Data output delay time from CLKOUT
↑
38
t
DKD
3
27
ns
Data output hold time (from CLKOUT
↓
)
39
t
HKDW
0
ns
ASTB
↑
delay time from WR
↑
40
t
DWSTH
0
ns
RAS
↓
delay time from CLKOUT
↑
41
t
DKRAL
nT
nT + 22
ns
RAS
↑
delay time from CLKOUT
↑
42
t
DKRAH
0
22
ns
RAS high-level width
43
t
WRAH
(n + 1)T – 15
ns
RAS
↑
delay time from WRH
↓
, WRL
↓
121
t
DWRAH
(N + 0.5)T – 10
ns
Address setup time (to RAS
↓
)
122
t
SARAL
nT – 12
ns
READY setup time (to CLKOUT
↓
)
44
t
SRYHK
18
ns
READY hold time (from CLKOUT
↓
)
45
t
HKRYL
12
ns
READY setup time (to CLKOUT
↓
)
46
t
SRYLK
18
ns
READY hold time (from CLKOUT
↓
)
47
t
HKRYH
12
ns
48
t
WRSL1
STOP release/power-on reset
30
ms
RESET low-level width
49
t
WRSL2
System reset
1000 + 2T
ns
NMI high-level width
50
t
WNIH
5
μ
s
NMI low-level width
51
t
WNIL
5
μ
s
INTPm setup time (to CLKOUT
↓
)
52
t
SIQK
m = 0 to 5
25
ns
INTPm high-level width
53
t
WIQH
m = 0 to 5
10T
ns
INTPm low-level width
54
t
WIQL
m = 0 to 5
10T
ns
POLL setup time (to CLKOUT
↓
)
55
t
SPLK
25
ns
HLDRQ setup time (to CLKOUT
↓
)
56
t
SHQK
25
ns
HLDAK
↓
delay time from CLKOUT
↑
57
t
DKHA
0
27
ns
HLDAK
↓
delay time from bus float
58
t
FCHA
0
ns
Bus output delay time from HLDAK
↑
59
t
DHAC
T – 22.5
ns
n :
N :
T :
Number of address wait states
Number of data wait states
t
CYK
Remark
Numbers in the Symbol column correspond to numbers in the timing charts.