
41
μ
PD70433
4.2
REFRESH FUNCTION
The following functions are provided to refresh DRAM and pseudo-SRAM.
Function to insert periodically a refresh cycle in a series of bus cycles
Refresh address output function to refresh DRAM and pseudo-SRAM
Function to generate a refresh cycle in hold mode and HALT mode.
Function to insert a wait state in a refresh cycle
4.2.1
Refresh Mode Register (RFM)
The RFM register is an 8-bit register to control refresh operation.
A refresh cycle can be selected from the time base counter output tap.
While a refresh request is held by another bus cycle if the next refresh request is generated, only the latter is valid.
The RFM register value after a reset is 77H.
4.2.2
Wait Control in Refresh Cycle
A wait state can be inserted in a refresh cycle. The specified number of wait states is inserted for memory block 4 by
the programmable wait control register (PWC0) or READY pin.
4.2.3
Refresh Address
Bus pins AD0 to AD15 and A16 to A19 are activated in a refresh cycle.
For each refresh cycle, the count is performed in one-address increments from x00000 to x1FFFFF in the case of the
external 8-bit bus width, and in two-address increments from x00001H to xFFFFF in the case of the external 16-bit bus width
(the minimum address is returned to after the maximum address).
After initialization by a reset, count-up is started from x00000H in the case of the external 8-bit bus width and x00001H
in the case of the external 16-bit bus width.
In the case of the external 16-bit bus width, the refresh address minimum address bit (A0) is fixed at “1” and the DEX
pin output is also fixed at “1”.
A20 to A23 are undefined in a refresh cycle.