參數(shù)資料
型號: UPD70433R-12
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V55PITM 16-BIT MICROPROCESSOR
中文描述: V55PITM 16位微處理器
文件頁數(shù): 132/166頁
文件大?。?/td> 772K
代理商: UPD70433R-12
132
μ
PD70433
AC CHARACTERISTICS (T
A
= –40 to +85
°
C, V
DD
= +5.0 V
±
10 %)
(1)
μ
PD70433-12
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
X1 input cycle time
1
t
CYX
40
250
ns
X1 input high-level width
2
t
WXH
15
ns
X1 input low-level width
3
t
WXL
15
ns
X1 input rise time
4
t
XR
10
ns
X1 input fall time
5
t
XF
10
ns
CLKOUT output cycle time
6
t
CYK
80
4000
ns
CLKOUT output high-level width
7
t
WKH
0.5T – 5
ns
CLKOUT output low-level width
8
t
WKL
0.5T – 5
ns
CLKOUT output rise time
9
t
KR
7
ns
CLKOUT output fall time
10
t
KF
7
ns
11
t
IR1
*1
10
ns
Input rise time
12
t
IR2
*2
20
ns
13
t
IF1
*1
10
ns
Input fall time
14
t
IF2
*2
20
ns
Output rise time
15
t
OR
10
ns
Output fall time
16
t
OF
10
ns
CLKOUT delay time from X1
118
t
DXK
X2: open
18
ns
Address delay time from CLKOUT
17
t
DKA
5
27
ns
18
t
HKA1
0
ns
Address hold time (from CLKOUT
)
19
t
HKA2
0
ns
Address float delay time from CLKOUT
20
t
FKA
t
HKA1
36
ns
Address setup time (to ASTB
)
21
t
SAST
(n + 0.5)T – 25
ns
Address hold time (from ASTB
)
22
t
HSTA
0.5T – 15
ns
ASTB
delay time from CLKOUT
23
t
DKSTL
0
22
ns
ASTB
delay time from CLKOUT
24
t
DKSTH
0
22
ns
ASTB high-level width
25
t
WSTH
(n + 1)T – 15
ns
RD
delay time from CLKOUT
26
t
DKRL
0
22
ns
RD
delay time from CLKOUT
27
t
DKRH
0
22
ns
RD low-level width
28
t
WRL
(N + 1.5)T – 15
ns
RD
delay time from address float
29
t
FARL
0
ns
Address delay time from RD
30
t
DRA
0.5T
ns
n :
N :
T :
Number of address wait states
Number of data wait states
t
CYK
* 1.
Other than
*2
RESET, P10 NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/R
X
D0/SB1/SI0, P32/T
X
C/SCK0, P33/
CTS0, P35/R
X
D1/SI1, P36/SCK1/CTS1
2.
Remark
Numbers in the Symbol column correspond to numbers in the timing charts.
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