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參數(shù)資料
| 型號： | UPD70433R-12 |
| 廠商： | NEC Corp. |
| 元件分類： | 16位微控制器 |
| 英文描述： | V55PITM 16-BIT MICROPROCESSOR |
| 中文描述： | V55PITM 16位微處理器 |
| 文件頁數(shù)： | 17/166頁 |
| 文件大?。?/td> | 772K |
| 代理商： | UPD70433R-12 |
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17
μ
PD70433
3.2
REGISTERS
The V55PI CPU has general register sets compatible with the V20 and V30 (native mode), and the V25 and V35. The
general register sets are mapped onto the register file space. These general register sets are also used as on-chip RAM,
and there can be a maximum of 16 register sets in bank form.
In addition, the V55PI has various special function registers for controlling on-chip peripheral hardware. These special
function registers are mapped onto memory space addresses 0FFE00H to 0FFFEFH.
3.2.1
Register Banks
The general register sets are mapped onto the register file space (in on-chip RAM). The general register sets are used
in a bank arrangement; each bank consists of 32 bytes and up to 16 banks can be set.
The CPU normally uses register bank 15 for program execution, and it is possible to switch to another bank automatically
by means of maskable hardware interrupt or software interrupt (BRKCS instruction). It is possible to return from the switched-
to register bank to the original register bank by means of the instruction for returning from an interrupt (RETRBI).
The register bank configuration is shown in Figure 3-1. The general register sets are mapped onto the area with an offset
of (+08H) to (+1FH) from the start address of each register bank. The word address from the start in a register bank is the
extended segment register (DS2) area. The vector PC/DS3 area is used to set the value to be loaded into the PC when
the register bank is switched, that is, the offset value of the start address of the interrupt service routine. This area is also
used as the extended segment register (DS3) area. The PSW save area is used to save the PSW when the register bank
is switched, and the PC save area is used to save the PC when the register bank is switched.
After a reset, register bank 15 is selected automatically. Also, segment register initialization after a reset is performed
for register bank 15 only.
The register file space onto which these general register sets are mapped can also be accessed as data memory by
addition of a special prefix instruction (IRAM:) to a memory manipulation instruction.
Of the 16 set register banks, banks 0 and 1 have macro service channels (parameter and work area for macro service)
allocated in duplicate.
相關PDF資料 |
PDF描述 |
|---|---|
| UPD70433R-16 | V55PITM 16-BIT MICROPROCESSOR |
| UPD70433GD-12-5BB | V55PITM 16-BIT MICROPROCESSOR |
| UPD70433GD-16-5BB | V55PITM 16-BIT MICROPROCESSOR |
| UPD70433GJ-12-3EB | V55PITM 16-BIT MICROPROCESSOR |
| UPD70433GJ-16-3EB | V55PITM 16-BIT MICROPROCESSOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD70433R-16 | 制造商:NEC 制造商全稱:NEC 功能描述:V55PITM 16-BIT MICROPROCESSOR |
| UPD705100 | 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER |
| UPD705100GJ-100-8 | 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER |
| UPD705100GJ-100-8EU | 制造商:NEC 制造商全稱:NEC 功能描述:V830TM 32-BIT MICROCONTROLLER |
| UPD705101 | 制造商:NEC 制造商全稱:NEC 功能描述:32-BIT MICROPROCESSOR |
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