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參數(shù)資料
| 型號： | TSB82AA2I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394b OHCI-LYNX CONTROLLER |
| 中文描述： | 的1394b OHCI的山貓控制器 |
| 文件頁數(shù)： | 83/104頁 |
| 文件大?。?/td> | 461K |
| 代理商： | TSB82AA2I |
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441
4.42 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous
transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3,
…
, 7). See Table 434 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Isochronous transmit context control
Type
RSCU
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
RSC
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Isochronous transmit context control
Type
RSC
R
R
RSU
RU
RU
R
R
R
R
R
RU
RU
RU
RU
RU
Default
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Isochronous transmit context control
Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only
200h + (16 * n)
set register
204h + (16 * n)
clear register
XXXX X0XXh
Default:
Table 434. Isochronous Transmit Context Control Register Description
BIT
31
FIELD NAME
cycleMatchEnable
TYPE
RSCU
DESCRIPTION
When bit 31 is set to 1, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 3016). The cycleMatch field (bits 3016) must match the low-order two bits of cycleSeconds
and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before
isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which
the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the
1394 Open Host Controller Interface Specification.
Once the context has become
active, hardware clears this bit.
3016
cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h (see Section 4.34,
Isochronous Cycle Timer Register
)
cycleSeconds field (bits 3125) and the cycleCount field (bits 2412). If bit 31 (cycleMatchEnable)
is set to 1, then this isochronous transmit DMA context becomes enabled for transmits when the
low-order two bits of the isochronous cycle timer register cycleSeconds field (bits 3125) and the
cycleCount field (bits 2412) value equal this field (cycleMatch) value.
15
run
RSC
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The TSB82AA2 device changes this bit only on a system (hardware)
or software reset.
1413
RSVD
R
Reserved. Bits 1413 return 0s when read.
12
wake
RSU
Software sets bit 12 to 1 to cause the TSB82AA2 device to continue or resume descriptor processing.
The TSB82AA2 device clears this bit on every descriptor fetch.
11
dead
RU
The TSB82AA2 device sets bit 11 to 1 when it encounters a fatal error, and clears the bit when
software clears bit 15 (run) to 0.
10
active
RU
The TSB82AA2 device sets bit 10 to 1 when it is processing descriptors.
95
RSVD
R
Reserved. Bits 95 return 0s when read.
40
event code
RU
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:
ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:
1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.
2. Bits 40 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.
3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) is set to 1.
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參數(shù)描述 |
|---|---|
| TSB82AA2IPGE | 功能描述:接口 - 專用 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TSB82AA2IPGEEP | 功能描述:1394 接口集成電路 Mil Enh 1394b OHCI- Lynx Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGE | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGEG4 | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2ZGW | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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