參數(shù)資料
型號(hào): TSB82AA2I
廠商: Texas Instruments, Inc.
英文描述: 1394b OHCI-LYNX CONTROLLER
中文描述: 的1394b OHCI的山貓控制器
文件頁(yè)數(shù): 42/104頁(yè)
文件大小: 461K
代理商: TSB82AA2I
322
3.26 GPIO Control Register
The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 324 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
GPIO control
Type
R
R
R
R
R
R
R
R
R/W
R
R/W
R/W
R
R
R
RWU
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
GPIO control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
GPIO control
Read/Write/Update, Read/Write, Read-only
FCh
0000 0000h
Table 324. GPIO Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3124
RSVD
R
Reserved. Bits 3124 return 0s when read.
23
INT_EN
R/W
When bit 23 is set to 1, a TSB82AA2 general-purpose interrupt event occurs on a level change of the
GPIO input. This event may generate an interrupt, with mask and event status reported through the
interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22,
Interrupt Mask Register
) and the
interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
).
22
RSVD
R
Reserved. Bit 22 returns 0 when read.
21
GPIO_INV
R/W
GPIO polarity invert. When bit 21 is set to 1, the polarity of GPIO is inverted.
20
GPIO_ENB
R/W
GPIO enable control. When bit 20 is set to 1, the output is enabled. Otherwise, the output is high
impedance.
1917
RSVD
R
Reserved. Bits 1917 return 0s when read.
16
GPIO_DATA
RWU
GPIO data. Reads from bit 16 return the logical value of the input to GPIO. Writes to this bit update the
value to drive to GPIO when the output is enabled.
150
RSVD
R
Reserved. Bits 150 return 0s when read.
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