參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁(yè)數(shù)： 25/104頁(yè)
文件大?。?/td> 461K
代理商： TSB82AA2I
35
3.4
Command Register
The command register provides control over the TSB82AA2 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
, as seen in the following bit descriptions. See Table 33 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Command
Type
R
R
R
R
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R/W
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Command
Read/Write, Read-only
04h
0000h
Table 33. Command Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
1511
RSVD
R
Reserved. Bits 1511 return 0s when read.
10
INT_DISABLE
R/W
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
This bit has been defined as part of the
PCI Local Bus Specification
(Revision 2.3).
9
FBB_ENB
R
Fast back-to-back enable. The TSB82AA2 device does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8
SERR_ENB
R/W
PCI_SERR enable. When bit 8 is set to 1, the TSB82AA2 PCI_SERR driver is enabled. PCI_SERR can
be asserted after detecting an address parity error on the PCI bus.
7
STEP_ENB
R
Address/data stepping control. The TSB82AA2 device does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6
PERR_ENB
R/W
Parity error enable. When bit 6 is set to 1, the TSB82AA2 device is enabled to drive PCI_PERR
response to parity errors through the PCI_PERR signal.
5
VGA_ENB
R
VGA palette snoop enable. The TSB82AA2 device does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
4
MWI_ENB
R/W
Memory write and invalidate enable. When bit 4 is set to 1, the TSB82AA2 device is enabled to
generate MWI PCI bus commands. If this bit is cleared, then the TSB82AA2 device generates memory
write commands instead.
3
SPECIAL
R
Special cycle enable. The TSB82AA2 function does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2
MASTER_ENB
R/W
Bus master enable. When bit 2 is set to 1, the TSB82AA2 device is enabled to initiate cycles on the PCI
bus.
1
MEMORY_ENB
R/W
Memory response enable. Setting bit 1 to 1 enables the TSB82AA2 device to respond to memory
cycles on the PCI bus. This bit must be set to access OHCI registers.
0
IO_ENB
R
I/O space enable. The TSB82AA2 device does not implement any I/O-mapped functionality; therefore,
bit 0 returns 0 when read.
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