參數(shù)資料
型號： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 64/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
422
Table 417. Interrupt Mask Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
21
cycle64Seconds
RSC
When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this 64-second-cycle interrupt mask enables
interrupt generation.
20
cycleSynch
RSC
When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this isochronous-cycle interrupt mask enables
interrupt generation.
19
phy
RSC
When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) are set to 1, this PHY-status-transfer interrupt mask enables interrupt
generation.
18
regAccessFail
RSC
When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this register-access-failed interrupt mask enables
interrupt generation.
17
busReset
RSC
When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this bus-reset interrupt mask enables interrupt
generation.
16
selfIDcomplete
RSC
When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this self-ID-complete interrupt mask enables
interrupt generation.
15
selfIDcomplete2
RSC
When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this second-self-ID-complete interrupt mask
enables interrupt generation.
1410
RSVD
R
Reserved. Bits 1410 return 0s when read.
9
lockRespErr
RSC
When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this lock-response-error interrupt mask enables
interrupt generation.
8
postedWriteErr
RSC
When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this posted-write-error interrupt mask enables
interrupt generation.
7
isochRx
RSC
When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this isochronous-receive-DMA interrupt mask
enables interrupt generation.
6
isochTx
RSC
When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this isochronous-transmit-DMA interrupt mask
enables interrupt generation.
5
RSPkt
RSC
When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) are set to 1, this receive-response-packet interrupt mask enables interrupt
generation.
4
RQPkt
RSC
When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) are set to 1, this receive-request-packet interrupt mask enables interrupt
generation.
3
ARRS
RSC
When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) are set to 1, this asynchronous-receive-response-DMA interrupt mask
enables interrupt generation.
2
ARRQ
RSC
When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21,
Interrupt Event Register
) are set to 1, this asynchronous-receive-request-DMA interrupt mask enables
interrupt generation.
1
respTxComplete
RSC
When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this response-transmit-complete interrupt mask
enables interrupt generation.
0
reqTxComplete
RSC
When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h (see
Section 4.21,
Interrupt Event Register
) are set to 1, this request-transmit-complete interrupt mask
enables interrupt generation.
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