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參數(shù)資料
| 型號： | TSB82AA2I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394b OHCI-LYNX CONTROLLER |
| 中文描述： | 的1394b OHCI的山貓控制器 |
| 文件頁數(shù)： | 26/104頁 |
| 文件大?。?/td> | 461K |
| 代理商： | TSB82AA2I |
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36
3.5
Status Register
The status register provides status over the TSB82AA2 interface to the PCI bus. All bit functions adhere to the
definitions in the
PCI Local Bus Specification
. See Table 34 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Status
Type
RCU
RCU
RCU
RCU
RCU
R
R
RCU
R
R
R
R
RU
R
R
R
Default
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Type:
Offset:
Default:
Status
Read/Clear/Update, Read-only
06h
0210h
Table 34. Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PAR_ERR
RCU
Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14
SYS_ERR
RCU
Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB82AA2 device has
signaled a system error to the host.
13
MABORT
RCU
Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB82AA2 device on the PCI bus
is terminated by a master abort.
12
TABORT_REC
RCU
Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB82AA2 device on the PCI bus is
terminated by a target abort.
11
TABORT_SIG
RCU
Signaled target abort. Bit 11 is set to 1 by the TSB82AA2 device when it terminates a transaction on the
PCI bus with a target abort.
109
PCI_SPEED
R
DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating
that the TSB82AA2 device asserts this signal at a medium speed on nonconfiguration cycle accesses.
8
DATAPAR
RCU
Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PCI_PERR was asserted by any PCI device including the TSB82AA2 device.
b. The TSB82AA2 device was the bus master during the data parity error.
c. Bit 6 (PERR_ENB) in the command register at offset 04h in the PCI configuration space
(see Section 3.4,
Command Register
) is set to 1.
7
FBB_CAP
R
Fast back-to-back capable. The TSB82AA2 device cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
6
UDF
R
User-definable features (UDF) supported. The TSB82AA2 device does not support the UDF;
therefore, bit 6 is hardwired to 0.
5
66MHZ
R
66-MHz capable. The TSB82AA2 device operates at a maximum PCI_CLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4
CAPLIST
R
Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power-management capabilities is implemented in this function.
3
INT_STATUS
RU
Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
in the command register (PCI offset 04h, see Section 3.4) is a 0 and this bit is a 1, is the function’s INTx
signal asserted. Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit. This bit has
been defined as part of the
PCI Local Bus Specification
(Revision 2.3).
20
RSVD
R
Reserved. Bits 20 return 0s when read.
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| TSB82AA2IPGE | 功能描述:接口 - 專用 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TSB82AA2IPGEEP | 功能描述:1394 接口集成電路 Mil Enh 1394b OHCI- Lynx Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGE | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGEG4 | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2ZGW | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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