參數(shù)資料
型號: TSB82AA2I
廠商: Texas Instruments, Inc.
英文描述: 1394b OHCI-LYNX CONTROLLER
中文描述: 的1394b OHCI的山貓控制器
文件頁數(shù): 16/104頁
文件大小: 461K
代理商: TSB82AA2I
24
The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see
Table 23 through Table 27). The terminal numbers are also listed for convenient reference.
Table 23. Power Supply Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NO.
GND
9, 22, 32, 43,
52, 63, 76, 81,
93, 103, 112,
122, 127, 137,
140
Ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
REG18
16
87
The REG18 terminals are connected to the internal 1.8-V core voltage. They provide a mechanism to
provide local bypass for the internal core voltage or to externally provide the 1.8 V to the core if the internal
regulator is disabled.
REG_EN
2
I
Regulator enable. When this terminal is low, the internal regulator is enabled and generates the 1.8-V
internal core voltage from the 3.3-V supply voltage. If it is disabled, then 1.8 V must be provided to the
REG18 terminals for normal operation.
VCC
8, 15, 31, 42,
62, 75, 86,
102, 126, 135,
139
3.3-V power supply terminals. A parallel combination of high frequency decoupling capacitors near each
terminal is suggested, such as 0.1
μ
F and 0.001
μ
F. Lower frequency 10-
μ
F filtering capacitors are also
recommended. They must be tied to a low-impedance point on the circuit board.
VCCP
21, 55, 91, 117
PCI signaling clamp voltage power input. PCI signals are clamped per the
PCI Local Bus Specification
. In
addition, if a 5-V ROM is used, then the VCCP terminal must be connected to 5 V.
Table 24. Reset and Miscellaneous Terminals
TERMINAL
I/O
DESCRIPTION
NAME
NO.
G_RST
7
I
Global power reset. This reset brings all of the TSB82AA2 internal registers to their default states, including those
registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. A valid clock
input (PCI_CLK) is required before deasserting G_RST to reset some device functionality. Additionally, G_RST
must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device.
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets to the
TSB82AA2 device. G_RST is designed to be a one-time power-on reset, and PCI_RST must be connected to the
PCI bus RST.
PCI_RST
6
I
PCI reset. When this bus reset is asserted, the TSB82AA2 device places all output buffers in a high-impedance
state and resets all internal registers except device power management context and vendor-specific bits initialized
by host power-on software. When PCI_RST is asserted, the device is completely nonfunctional. This terminal
must be connected to PCI bus RST.
MFUNC
1
I/O
Multifunction terminal. MFUNC is a multifunction terminal whose function is selected via the multifunction select
register:
Bits 20
Function
000
General-purpose input/output (GPIO)
001
CYCLEIN
010
CYCLEOUT
011
PCI_CLKRUN
100111
Reserved
SCL
3
I/O
Serial clock. This terminal provides the SCL serial clock signaling.
ROM is implemented: Connect terminal 3 to the SCL terminal on the ROM; the 2.7-k
resistor pulls this signal
to the ROM VCC. (SDA is implemented as open-drain.)
ROM is not implemented. Connect terminal 3 to ground with a 220-
resistor.
SDA
4
I/O
Serial data. This terminal provides the SDA serial data signaling. This terminal is sampled at G_RST to determine
if a serial ROM is implemented; thus if no ROM is implemented, then this terminal must be connected to ground.
ROM is implemented: Connect terminal 4 to the SDA terminal on the ROM; the 2.7-k
resistor pulls this signal
to the ROM VCC. (SDA is implemented as open-drain.)
ROM is not implemented. Connect terminal 4 to ground with a 220-
resistor.
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