參數(shù)資料
型號(hào): TSB82AA2I
廠商: Texas Instruments, Inc.
英文描述: 1394b OHCI-LYNX CONTROLLER
中文描述: 的1394b OHCI的山貓控制器
文件頁數(shù): 50/104頁
文件大?。?/td> 461K
代理商: TSB82AA2I
48
4.7
Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset
FFFF F000 0400h. See Table 46 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Configuration ROM header
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Configuration ROM header
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Default:
Configuration ROM header
Read/Write
18h
0000 XXXXh
Table 46. Configuration ROM Header Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3124
info_length
R/W
IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is set to 1.
2316
crc_length
R/W
IEEE 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller control
register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is set to 1.
150
rom_crc_value
R/W
IEEE 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16,
Host Controller Control Register
) is set to
1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, then
this field is loaded from the serial EEPROM.
4.8
Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the constant
3133 3934h, which is the ASCII value of 1394.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Bus identification
R
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
1
1
0
0
0
1
0
0
1
1
0
0
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Bus identification
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
1
1
1
0
0
1
0
0
1
1
0
1
0
0
Register:
Type:
Offset:
Default:
Bus identification
Read-only
1Ch
3133 3934h
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