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參數(shù)資料
| 型號： | TSB82AA2I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394b OHCI-LYNX CONTROLLER |
| 中文描述： | 的1394b OHCI的山貓控制器 |
| 文件頁數(shù)： | 71/104頁 |
| 文件大?。?/td> | 461K |
| 代理商： | TSB82AA2I |
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429
4.31 Link Control Register
The link control set/clear register provides the control flags that enable and configure the link core protocol portions
of the TSB82AA2 device. It contains controls for the receiver and cycle timer. See Table 424 for a complete
description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Link control
Type
R
R
R
R
R
R
R
R
R
RSC
RSCU
RSC
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Link control
Type
R
R
R
R
R
RSC
RSC
R
R
RS
R
R
R
R
R
R
Default
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Link control
Read/Set/Clear/Update, Read/Set/Clear, Read/Set, Read-only
E0h
set register
E4h
clear register
00X0 0X00h
Default:
Table 424. Link Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3123
RSVD
R
Reserved. Bits 3123 return 0s when read.
22
cycleSource
RSC
When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll
over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches
3072 cycles of the 24.576-MHz clock (125
μ
s).
When bit 21 is set to 1 and the PHY device has notified the TSB82AA2 device that PHY device is
root, the TSB82AA2 device generates a cycle start packet every time the cycle timer rolls over, based
on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynx accepts received
cycle start packets to maintain synchronization with the node which is sending them. Bit 21 is
automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI offset
80h/84h (see Section 4.21,
Interrupt Event Register
) is set to 1. Bit 21 cannot be set to 1 until bit 25
(cycleTooLong) is cleared.
21
cycleMaster
RSCU
20
CycleTimerEnable
RSC
When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over
at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle
timer offset does not count.
1911
RSVD
R
Reserved. Bits 1911 return 0s when read.
10
RcvPhyPkt
RSC
When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if
the AR request context is enabled. This bit does not control receipt of self-ID packets.
9
RcvSelfID
RSC
When bit 9 is set to 1, the receiver accepts incoming self-ID packets. Before setting this bit to 1,
software must ensure that the self-ID buffer pointer register contains a valid address.
87
RSVD
R
Reserved. Bits 87 return 0s when read.
6
tag1SyncFilterLock
RS
When this bit is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive context match register (see
Section 4.46,
Isochronous Receive Context Match Register
) is set to 1 for all isochronous receive
contexts. When this bit is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context match
register has Read/Write access. This bit is cleared when G_RST is asserted.
50
RSVD
R
Reserved. Bits 50 return 0s when read.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB82AA2IPGE | 功能描述:接口 - 專用 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| TSB82AA2IPGEEP | 功能描述:1394 接口集成電路 Mil Enh 1394b OHCI- Lynx Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGE | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2PGEG4 | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB82AA2ZGW | 功能描述:1394 接口集成電路 OHCI-Lynx Controller RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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