參數(shù)資料
型號： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 81/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
439
4.40 Asynchronous Context Control Register
The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See
Table 432 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Asynchronous context control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Asynchronous context control
Type
RSCU
R
R
RSU
RU
RU
RU
R
RU
RU
RU
RU
RU
RU
RU
RU
Default
0
0
0
X
0
0
0
0
X
X
X
X
X
X
X
X
Register:
Type:
Offset:
Asynchronous context control
Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read-only
180h
set register
[ATRQ]
184h
clear register
[ATRQ]
1A0h
set register
[ATRS]
1A4h
clear register
[ATRS]
1C0h
set register
[ARRQ]
1C4h
clear register
[ARRQ]
1E0h
set register
[ARRS]
1E4h
clear register
[ARRS]
0000 X0XXh
Default:
Table 432. Asynchronous Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
RSVD
R
Reserved. Bits 3116 return 0s when read.
15
run
RSCU
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The TSB82AA2 device changes this bit only on a system (hardware)
or software reset.
1413
RSVD
R
Reserved. Bits 1413 return 0s when read.
12
wake
RSU
Software sets bit 12 to 1 to cause the TSB82AA2 device to continue or resume descriptor processing.
The TSB82AA2 device clears this bit on every descriptor fetch.
11
dead
RU
The TSB82AA2 device sets bit 11 when it encounters a fatal error, and clears the bit when software
clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide unique
contextControl.dead functionality. See Section 7.7 in the
1394 Open Host Controller Interface
Specification
(Revision 1.1) for more information.
10
active
RU
The TSB82AA2 device sets bit 10 to 1 when it is processing descriptors.
9
betaFrame
RU
Bit 9 is set to 1 when the PHY indicates that the received packet is sent in Beta format. A response
to a request sent using Beta format also uses Beta format.
8
RSVD
R
Reserved. Bit 8 returns 0 when read.
75
spd
RU
This field indicates the speed at which a packet was received or transmitted and only contains
meaningful information for receive contexts. This field is encoded as:
000 = 100M bits/sec
001 = 200M bits/sec
010 = 400M bits/sec
011 = 800M bits/sec
All other values are reserved.
40
eventcode
RU
This field holds the acknowledge sent by the link core for this packet or holds an internally generated
error code if the packet was not transferred successfully.
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