參數(shù)資料
型號(hào)： TSB82AA2I
廠商： Texas Instruments, Inc.
英文描述： 1394b OHCI-LYNX CONTROLLER
中文描述： 的1394b OHCI的山貓控制器
文件頁數(shù)： 73/104頁
文件大?。?/td> 461K
代理商： TSB82AA2I
431
4.33 PHY Layer Control Register
The PHY layer control register reads from or writes to a PHY register. See Table 426 for a complete description of
the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
PHY layer control
Type
RU
R
R
R
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
RU
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
PHY layer control
Type
RWU
RWU
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
PHY layer control
Read/Write/Update, Read/Write, Read/Update, Read-only
ECh
0000 0000h
Table 426. PHY Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
rdDone
RU
Bit 31 is cleared to 0 by the TSB82AA2 device when either bit 15 (rdReg) or bit 14 (wrReg) is set to
1. This bit is set to 1 when a register transfer is received from the PHY device.
3028
RSVD
R
Reserved. Bits 3028 return 0s when read.
2724
rdAddr
RU
This field is the address of the register most recently received from the PHY device.
2316
rdData
RU
This field is the contents of a PHY register that has been read.
15
rdReg
RWU
Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
14
wrReg
RWU
Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
1312
RSVD
R
Reserved. Bits 1312 return 0s when read.
118
regAddr
R/W
This field is the address of the PHY register to be written or read.
70
wrData
R/W
This field is the data to be written to a PHY register and is ignored for reads.
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