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參數(shù)資料
| 型號(hào)： | TDAT04622 |
| 英文描述： | TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces |
| 中文描述： | TDAT的SONET / SDH 155/622/2488 Mbits /秒數(shù)據(jù)接口 |
| 文件頁數(shù)： | 99/310頁 |
| 文件大小： | 4628K |
| 代理商： | TDAT04622 |
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Agere Systems Inc.
71
Data Sheet
May 2001
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Functional Description
(continued)
Data Engine (DE) Block
(continued)
Receive Data Engine
Receive Sequencer.
The receive sequencer demaps SONET framing to four logical channels, performs the phys-
ical channel byte alignment and packing, and performs appropriate payload clock domain transfer. The receive
sequencer must be provisioned properly for correct operation. There are six registers that are fixed for each partic-
ular mode of operation (STS-3/STM-1, STS-12/STM-4, or STS-48/STM-16) and must not be modified
(SEQ_CTRL, INIT_CNTS, OH_MARKER_LO, OH_MARKER_HI, SOH_MARKER_LO, SOH_MARKER_HI). See
the register descriptions for details, page 214. Also, the appropriate time slots must be provisioned for the rate of
the payload expected for each channel. This is done via the registers Rx_TS[1
—
12] (see register descriptions,
page 219). An example of how to configure this for STS-48c mode is shown in the section on configuring the trans-
mit/receive sequencer (see Transmit Data Engine section, page 78).
ATM Cell Processor.
The cell processor performs ATM cell delineation using the ATM header error correction
(HEC) field found in the cell header. The HEC is a CRC-8 calculation over the first four octets (total of 32 bits) of
the ATM cell header. If the TDAT042G5 is in bit-synchronous mode (data is not byte-aligned), 32 separate HEC
calculations are performed to delineate an ATM cell. If the TDAT042G5 is in byte-synchronous mode (data is byte-
aligned), four separate HEC calculations are performed to delineate an ATM cell. An alpha-delta counter is used to
track the processor
’
s ability to frame the ATM cells consistently. When a certain level of confidence is reached
(defined by the programmable delta counter threshold), the frame is declared in
sync
state, and data is passed to
subsequent blocks. If the framer is unable to frame ATM cells over a few cell periods (defined by the programma-
ble delta counter threshold), the framer resumes
hunt
state.
In SONET mode, the processor performs optional X
43
unscrambling of the payload. Because the X
43
scrambler is
self-synchronizing, the framer needs no assistance from the data in order to synchronize the scrambler. The
TDAT042G5 also supports an X
31
scrambler, compliant with I.432, which is mainly used for packet-over-fiber
applications. The state diagram for the X
31
scrambler is shown in Figure 14 on page 72. The X
31
scrambler uses
an x
31
+ x
28
+ 1 polynomial to scramble the data. Unlike the X
43
scrambler, the X
31
scrambler does not self-
synchronize based upon the data it receives. Thus, one-bit samples of the scrambler output are sent on the trans-
mit side and compared with the scrambler samples on the receive side every 212 bits. If the samples do not match,
the receive-side scrambler is adjusted to converge with the transmit-side scrambler. This process continues until a
certain level of confidence in the scrambler synchronization is achieved. In the X
31
mode, the ATM cell processor
does not send out any output until both the framer and the scrambler are synchronized, whereas in X
31
mode, only
the framer needs to be synchronized.
Idle ATM cells, which contain no real data, can be either left in or removed from the bit stream. The idle cell header
description can be configured, though it is set to a default value (0x00000001). ATM cells can also be filtered if the
header contents match a provisioned match register after masking with a provisionable mask register. This allows
filtering based on the contents of the GFC, PTI, and CLP fields of the header. Optionally, ATM cells may be
dropped if uncorrectable HEC errors are detected. Incoming single-bit ATM header errors can be corrected and the
cells may be passed through or dropped, depending on the software configuration.
The data engine processes only standard 53-byte ATM cells. However, the UTOPIA block processes 52-byte, 53-
byte, 54-byte, and 56-byte cells, and interfaces these to the data engine. (See UTOPIA (UT) Interface Block,
page 86, for details).
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TDAT12622-BA23 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT12622-BA23-DB | 制造商:LSI Corporation 功能描述:SONET/SDH Interface 792-Pin BGA |
| TDAT161G2-BA23 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT162G52 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT162G52-3BA | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
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