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參數(shù)資料
| 型號： | TDAT04622 |
| 英文描述： | TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces |
| 中文描述： | TDAT的SONET / SDH 155/622/2488 Mbits /秒數(shù)據(jù)接口 |
| 文件頁數(shù)： | 21/310頁 |
| 文件大?。?/td> | 4628K |
| 代理商： | TDAT04622 |
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Agere Systems Inc.
19
Advisory
May 2001
for Version 1 and 1A of the Device
TDAT042G5 Device Advisory
UTOPIA (UT)
(continued)
I
The interface can drain an entire FIFO at a rate of 400 Mbytes/s. To drain 256 bytes, it requires a maximum of
(256 / 400,000,000) = 0.64
μ
s to drain a FIFO that is completely full. To drain all four FIFOs, it requires
(0.64 x 4) = 2.56
μ
s total
.
For data to be efficiently removed from each of the Rx FIFOs, a round-robin extraction method must be employed
since the RxPAB and RxPAD signals are not available for direct status polling. Since it requires a worst case total of
3.2922
μ
s to fill a FIFO, the master must service all FIFOs in a manner such that it does not allow any particular
FIFO to fill and hence overflow. Assuming equal servicing of each FIFO, the master must therefore not service any
particular FIFO for longer than (3.2922 / 4) = 0.8231
μ
s. This also must account for any dead cycles in a cycling
between channels and any dead cycles on a particular channel (single dead cycle between EOP and SOP).
When servicing four FIFOs, there is a maximum clock cycle penalty for switching between channels. For two-cycle
mode, this penalty is a maximum of four UTOPIA master clock cycles; so to switch between all four channels, a
total of up to sixteen master clock cycles may be required to perform all the switching. The value of four is worst
case, and in some cases this can be as low as one cycle. The value of four results from the case where the FIFO
drains while servicing that channel, which will be common when draining at the 100 MHz frequency. In that case,
the master must first see that the FIFO has drained by observing that RxPAA is invalid on the last cycle while drain-
ing the FIFO (best case is one cycle lost). It must then deactivate RxENB and place a new channel address on the
address bus on the following cycle (best case is one cycle lost). It must then activate RxENB for the new channel
on the following cycle and have TDAT sample RxENB low (best case is one cycle lost). The TDAT will then output
data two cycles later when using a PA response mode of two cycles (one cycle lost with data output on second
cycle). Any additional delays by the master must be added to these to calculate a worst-case condition. The best-
case condition occurs when the master stops the data flow when there are still more than two data items contained
within the FIFO. In this case, the master deactivates RxENB at some predetermined maximum 32-bit word drain
value, where the PA response on the cycle prior to deactivation had valid data. For two-cycle mode, two additional
data items will be output from the FIFO for that particular channel, if available. The master deactivates RxENB,
places the new channel address on the FIFO, and activates RxENB. On the cycle where RxENB is activated, the
last valid data item from the previous channel may be output (best case), and one dead cycle will follow this before
data for the following selected channel is output.
Given the information above, assume the worst case of four cycles between channel switching. Also assume the
FIFOs are filling at a worst-case rate, 3.2922
μ
s/FIFO. Assume the master is draining each FIFO using the 32-bit,
100 MHz, A/B, UTOPIA interface. Assume the master extracts a maximum of thirty 32-bit words (120 bytes) from
each FIFO before switching to an alternate channel. This requires (30 x 10) = 300 ns/FIFO, and assume that it
takes the worst-case four clock cycles to switch to alternate channels. Therefore, the total servicing time per FIFO
is (300 + 4 x 10) = 340 ns/channel, and the total servicing time per four channels is (4 x 340) = 1.36
μ
s per round
robin servicing of all four channels. At this round-robin rate, a maximum of 120 bytes are serviced per channel per
1.360
μ
s interval; so to service the total bytes per channel (74.88 Mbytes/s), it requires a total of 0.849 seconds,
which is sufficient bandwidth to service all channels.
Since the FIFOs fill at the maximum rate of 1 byte/13.355 ns, each FIFO will fill to a depth of 102 bytes in the
1.360
μ
s interval between channel servicing. This is well below the overflow threshold, which is set by the user to a
value near the top of the FIFO (high watermark, 0x36 (216 bytes) default) and is below the number of bytes ser-
viced by the master per channel per round-robin servicing (120 bytes). Each customer’s servicing characteristics
will depend on the master’s behavior and how fast it performs the channel switching. If it cannot switch in the worst-
case, four-cycle manner described above, performance will degrade.
One item not accounted for in the above analysis is the fact that TDAT may place a dead cycle between packets (in
CRC and PPP modes, not in HDLC mode). In this case, there can be a maximum of three dead cycles per FIFO
(assuming 40-byte packets worst case and 102 bytes in FIFO between round-robin cycle). This will be taken up by
the slack provided above, where (102 bytes + 4 bytes/dead cycle x 3 dead cycles) = 114 bytes, which still falls
below the servicing rate of 120 bytes per round-robin servicing.
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|---|---|
| TDAT12622-BA23 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
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| TDAT162G52 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT162G52-3BA | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
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