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參數(shù)資料
| 型號(hào)： | TDAT04622 |
| 英文描述： | TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces |
| 中文描述： | TDAT的SONET / SDH 155/622/2488 Mbits /秒數(shù)據(jù)接口 |
| 文件頁(yè)數(shù)： | 117/310頁(yè) |
| 文件大?。?/td> | 4628K |
| 代理商： | TDAT04622 |
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Agere Systems Inc.
89
Data Sheet
May 2001
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Functional Description
(continued)
UTOPIA (UT) Interface Block
(continued)
UT Receive Input Path (Ingress)
The UTOPIA Rx interface is designed to accommodate ATM cells as well as packet traffic. While the standard
UTOPIA interface transmits and receives ATM cells, this interface has been enhanced to carry non-ATM traffic.
The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2 (U2+), UTOPIA
Level 3 (U3) in 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 8-bit mode or 32-bit mode.
In the receive direction, data arrives and is sent to one of four channels (A through D). Each channel buffers data
independently and, when sufficient data has been stored in its FIFO, sends the data out of the channel via its UTO-
PIA interface. There are four paths inside the UT core, corresponding to one path per channel. These paths are
labeled A to D. When using 32-bit modes, only the control signals of interface A and size signals of interfaces A
and B are used.
Note:
32-bit mode is supported using channels A and B only. When 32-bit mode is selected, channels B, C, and D
must be configured to be idle (channel B will be under the control of channel A in 32-bit mode).
In normal mode, data arrives into the ingress channel, and control and data information are written into the FIFO.
The data is extracted from the FIFO, and word-aligned on the first byte of data. After word alignment, the data is
sent out of the device via the UTOPIA interface.
Note:
The start of packets must be word-aligned, and there can only be one packet per word (required by the defi-
nition of the UTOPIA interface).
FIFO.
The 256-byte UTOPIA Rx FIFO is responsible for buffering data from the DE block to be sent to the UTOPIA
interface. The FIFO accommodates four ATM cells or 256 bytes of packet data. In STS-48/STM-16, only one
256-byte FIFO is used. The FIFO is required to manage the asynchronous nature of the UTOPIA interface. Over-
flow will only occur if the master device connected to the UTOPIA interface is having congestion problems. When
overflow occurs and head of line discard is performed, it is possible that part of one packet may be appended to
another (if, for example, an end of packet is discarded along with the data at the head of the FIFO). Because this is
not a desirable operation, it is necessary to discard until the start of the next packet is observed. Data is read from
the FIFO when there is sufficient data in the FIFO. Upon overflow, the RxERR and RxEOP signals are asserted to
indicate to the master the corruption of the current packet.
Sufficient data is defined to be a minimum amount of data in the FIFO (a programmable threshold, low watermark),
or at least one end of packet stored in the FIFO. If the FIFO overflows, the block is responsible for discarding data
until the next start of packet. When this occurs, an alarm is raised. Underflow in the receive direction can occur
when there is no data, or if only part of a packet has arrived and has been transmitted, and is normal behavior.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TDAT12622-BA23 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT12622-BA23-DB | 制造商:LSI Corporation 功能描述:SONET/SDH Interface 792-Pin BGA |
| TDAT161G2-BA23 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT162G52 | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
| TDAT162G52-3BA | 制造商:AGERE 制造商全稱:AGERE 功能描述:MARS㈢2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface |
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