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參數(shù)資料
| 型號(hào)： | TDAT04622 |
| 英文描述： | TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces |
| 中文描述： | TDAT的SONET / SDH 155/622/2488 Mbits /秒數(shù)據(jù)接口 |
| 文件頁(yè)數(shù)： | 55/310頁(yè) |
| 文件大?。?/td> | 4628K |
| 代理商： | TDAT04622 |
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Agere Systems Inc.
27
Data Sheet
May 2001
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Pin Information
(continued)
Table 4. Pin Descriptions
—
TOH Interface Signals
* I
u
= I
d
= 50 k
, where I
u
= internal pull-up resistance and I
d
= internal pull-down resistance.
Pin
AK3
Symbol
RxREF
Type
3.3 V
I/O
*
O
Name/Description
Receive Line Frame.
This output provides the receive 8 kHz
frame reference for external timing needs. RxREF is derived from
one of the received line clocks (user-selectable). It is a 50% duty
cycle clock when TDAT042G5 is in frame. This signal may be
used to implement line timing on a SONET ring. When not provi-
sioned, this signal must not be used. RxREF is valid only when
the SONET framer is in frame. Upon LOC or LOF, RxREF is
present but is free running. Because jitter may be present on this
signal when the device goes into and out of an LOC or LOF state,
it should not be used as a reference for TxFSYNCP/N.
Receive TOH Interface Clock.
This clock is nominally a
5.184 MHz (STS-3/STM-1) or 20.736 MHz (STS-12/STM-4,
STS-48/STM-16) clock which provides timing for circuitry that
receives and externally processes the receive transport overhead
bytes. The duty cycle of the clock is not 50% (see Figure 49 and
Figure 50, page 272). In STS-48/STM-16 mode, all four of these
clocks are active.
Receive TOH Interface Data.
This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the receive transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1
—
D3, H1
—
H3, K1, K2,
D4
—
D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
can be used by external circuitry to process the TOH bytes.
RxTOHD is updated on the falling edge of RxTOHCK. In STS-48/
STM-16 mode, RxTOHD[A] contains all currently defined TOH
bits except for M1, which is located in RxTOHD[C].
Receive TOH Interface Frame.
This 8 kHz framing signal is used
to locate the individual receive transport overhead bits in the
RxTOHD bit stream. RxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is present on
the RxTOHD output. RxTOHF is updated on the falling edge of
RxTOHCK.
Transmit TOH Interface Clock.
This clock is nominally a
5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4,
STS-48/STM-16) clock which provides timing for circuitry that
externally generates and transmits the transmit transport over-
head bytes for inclusion in the transmit data stream. The duty
cycle of the clock is not 50% (see Figure 48, pag e271).
Transmit TOH Interface Data.
This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the transmit transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1
—
D3, H1
—
H3, K1, K2,
D4
—
D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
is generated by external circuitry for custom TOH byte definitions.
TxTOHD is sampled on the rising edge of TxTOHCK.
Transmit TOH Interface Frame.
This 8 kHz framing signal is
used to align the individual transmit transport overhead bits in the
TxTOHD bit stream. TxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is expected
on the TxTOHD input. TxTOHF is updated on the falling edge of
TxTOHCK.
AL7
AL6
AL4
AK5
RxTOHCK[D]
RxTOHCK[C]
RxTOHCK[B]
RxTOHCK[A]
3.3 V
O
AN7
AM6
AM5
AL2
RxTOHD[D]
RxTOHD[C]
RxTOHD[B]
RxTOHD[A]
3.3 V
O
AP6
AN5
AL3
AK4
RxTOHF[D]
RxTOHF[C]
RxTOHF[B]
RxTOHF[A]
3.3 V
O
AJ2
TxTOHCK
3.3 V
O
AK2
AJ5
AJ4
AJ3
TxTOHD[D]
TxTOHD[C]
TxTOHD[B]
TxTOHD[A]
3.3 V
(5 V tolerant)
I
u
AH5
TxTOHF
3.3 V
O
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