參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 81/140頁
文件大?。?/td> 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
81
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
Each character is stored in a matrix of 12 x 16 x 1 (V x H x planes), this allows for all possible character matrices
to be defined within a single location.
Micro Address
8800
80h
Figure 38 Organisation of DRC RAM
D
EFINING
C
HARACTERS
The DRC RAM is mapped into the 80C51 RAM address space and starts at location 8800H. The character
matrix is 12 bits wide and therefore requires two bytes to be written for each word, the first byte (even
addresses), addresses the lower 8 bits and the lower nibble of the second byte (odd addresses) addresses the
upper 4 bits.
For characters of 9, 10 or 16 lines high the pixel information starts in the first address and continues sequentially
for the required number of address.
Characters of 13 lines high are defined with an initial offset of 1 address, this is to allow for correct generation
of fringing across boundaries of clustered characters (see Figure 39). The characters continue sequentially for
13 lines after which a further line can again be used for generation of correct fringing across boundaries of
clustered characters.
CHAR 1
CHAR 2
CHAR 30
CHAR 31
CHAR 0
A
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
CHAR 0
Address
12 bits
881F
8820
883F
8840
885F
8BFF
8BE0
8BDF
8BC0
Char Code
81h
82h
9Eh
9Fh
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