參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 40/140頁
文件大小： 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
40
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
I2C Port Selection
The selection of the SCL0/SDA0 port is done using TXT21.I2C PORT0 bit. When the port is enabled any
information transmitted from the device goes onto the enabled port. Any information transmitted to the device
can only be acted on if the port is enabled.
LED Support
Port pins P0.5 and P0.6 have an 8mA current sinking capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for additional buffering circuitry.
Memory Interface
The memory interface controls access to the embedded DRAM, refreshing of the DRAM and page clearing. The
DRAM is shared between Data Capture, Display and Microcontroller sections. The Data Capture section uses
the DRAM to store acquired information that has been requested. The Display reads from the DRAM information
and converts it into RGB values. The Microcontroller uses the DRAM as embedded auxiliary RAM and to
generate OSD.
Memory Structure
The memory is partitioned into two distinct areas, the dedicated auxiliary RAM area, and the Display RAM area.
The Display RAM area when not being used for Data Capture or Display can be used as an extension to the
auxiliary RAM area.
A
UXILIARY
RAM
The auxiliary RAM is not initialised at power up. The contents of the auxiliary RAM are maintained during Idle
mode, but are lost if Power Down mode is entered.
D
ISPLAY
RAM
The Display RAM is initialised on power up to a value 20H. The contents of the Display RAM are maintained
when entering Idle mode. If Idle mode is exited using an Interrupt then the contents are unchanged, if Idle mode
is exited using a RESET then the Display RAM is initialised to 20H.
The size of the DRAM can be any value up to 2K.
Memory Mapping
The dedicated auxiliary RAM area occupies a maximum of 2K, with an address range from 0000H to 07FFH.The
Display RAM occupies a maximum of 10K with an address range from 2000H to 47FFH for TXT mode and
8000H to 86FFH for CC mode (see Figure 15). The two modes although having different address ranges occupy
physical the same DRAM area.
When not utilising the display memory, up to 12K is available for use as dedicated auxiliary RAM.
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