
Philips Semiconductors
Preliminary specification
1999 Sep 28
27
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
OSD LANG
ENABLE
Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14
OSD LAN<2:0>
Alternative C12/C13/C14 bits for use with OSD menus
TXT21
DISP
LINES<1>
DISP
LINES<0>
CHAR
SIZE<1>
CHAR
SIZE<0>
0
CC ON
I2C PORT0
CC/TXT
02H
DISP
LINES<1:0>
The number of display lines per character row.
00 - 10 lines per character (defaults to 9 lines in 525 mode)
01 - 13 lines per character
10 - 16 lines per character
11 - reserved
CHAR
SIZE<1:0>
Character matrix size.
00 - 10 lines per character (matrix 12x10)
01 - 13 lines per character (matrix 12x13)
10 - 16lines per character (matrix 12x16)
11 - reserved
CCON
0 - Closed Caption acquisition off
1 - Closed Caption acquisition on
I2C PORT0
0 - disable I2C PORT0
1 - enable I2C PORT0 selection (P1.7/SDA0, P1.6/SCL0)
CC/TXT
0 - Display configured for TXT mode
1 - Display configured for CC mode
WDT
WDV<7>
WDV<6>
WDV<5>
WDV<4>
WDV<3>
WDV<2>
WDV<1>
WDV<0>
00H
WDv<7:0>
Watch Dog Timer period
WDTKEY
WKEY<7>
WKEY<6>
WKEY<5>
WKEY<4>
WKEY<3>
WKEY<2>
WKEY<1>
WKEY<0>
00H
WKEY<7:0>
Watch Dog Timer Key
Note: Must be set to 55H to disable Watch dog timer when active
WSS1
0
0
0
WSS<3:0>
ERROR
WSS<3>
WSS<2>
WSS<1>
WSS<0>
00H
WSS<3:0>
ERROR
0 - No error in WSS<3:0>
1 - Error in WSS<3:0>
WSS<3:0>
Signalling bits to define aspect ratio (group 1)
WSS2
0
0
0
WSS<7:4>
ERROR
WSS<7>
WSS<6>
WSS<5>
WSS<4>
00H
WSS<7:4>
ERROR
0 - No errors in WSS<7:4>
1 - Error in WSS<7:4>
WSS<7:4>
Signalling bits to define enhanced services (group 2)
WSS3
WSS<13:11<
ERROR
WSS<13>
WSS<12>
WSS<11>
WSS<10:8>
ERROR
WSS<10>
WSS<9>
WSS<8>
00H
WSS<13:11>
ERROR
0 - No error in WSS<13:11>
1 - Error in WSS<13:11>
WSS<13:11>
Signalling bits to define reserved elements (group 4)
WSS<10:8>
ERROR
0 - No error in WSS<10:8>
1 - Error in WS<10:8>
WSS<10:8>
Signalling bits to define subtitles (group 3)
XRAMP
XRAMP<7>
XRAMP<6>
XRAMP<5>
XRAMP<4>
XRAMP<3>
XRAMP<2>
XRAMP<1>
XRAMP<0>
00H
XRAMP<7:0>
Internal RAM access upper byte address
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 4 SFR Bit description