參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 15/140頁
文件大?。?/td> 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
15
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
Figure 10 Lower 128 Bytes of Internal RAM
The upper 128 bytes is not allocated for any special area or functions.
SFR Memory
The Special Function Register (SFR) space is used for Port latches, timer, peripheral control, acquisition control,
display control, etc. These register can only be accessed by direct addressing. Sixteen of the addresses in the
SFR space are both byte and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0H
or 8H
.
A summary of the SFR map in address order is shown in Table 3.
.
ADD
R/W
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
80H
R/W
P0
-
P0<6>
P0<5>
-
-
-
-
-
81H
R/W
SP
SP<7>
SP<6>
SP<5>
SP<4>
SP<3>
SP<2>
SP<1>
SP<0>
82H
R/W
DPL
DPL<7>
DPL<6>
DPL<5>
DPL<4>
DPL<3>
DPL<2>
DPL<1>
DPL<0>
83H
R/W
DPH
DPH<7>
DPH<6>
DPH<5>
DPH<4>
DPH<3>
DPH<2>
DPH<1>
DPH<0>
87H
R/W
PCON
0
ARD
RFI
WLE
GF1
GF0
PD
IDL
88H
R/W
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H
R/W
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
R/W
TL0
TL0<7>
TL0<6>
TL0<5>
TL0<4>
TL0<3>
TL0<2>
TL0<1>
TL0<0>
8BH
R/W
TL1
TL1<7>
TL1<6>
TL1<5>
TL1<4>
TL1<3>
TL1<2>
TL1<1>
TL1<0>
Table 3 SFR Map
Bank Select
Bits in PSW
00H
08H
10H
0FH
18H
20H
1FH
07H
17H
2FH
11 = BANK3
7FH
10 = BANK2
01 = BANK1
00 = BANK0
Bit Addressable Space
(
Bit Addresses 0-7F)
4 Banks of
8 Registers
R0 - R7
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