參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 22/140頁
文件大?。?/td> 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
22
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
IT1
Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.
IE0
Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
IT0
Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts
TDACH
TPWE
1
TD<13>
TD<12>
TD<11>
TD<10>
TD<9>
TD<8>
40H
TPWE
0 - Disable Tuning Pulse Width Modulator
1 - Enable Tuning Pulse Width Modulator
TD<13:8>
Tuning Pulse Width Modulator High Byte
TDACL
TD<7>
TD<6>
TD<5>
TD<4>
TD<3>
TD<2>
TD<1>
TD<0>
00H
TD<7:0>
Tuning Pulse Width Modulator Low Byte
TH0
TH0<7>
TH0<6>
TH0<5>
TH0<4>
TH0<3>
TH0<2>
TH0<1>
TH0<0>
00H
TH0<7:0>
Timer 0 high byte
TH1
TH1<7>
TH1<6>
TH1<5>
TH1<4>
TH1<3>
TH1<2>
TH1<1>
TH1<0>
00H
TH1<7:0>
Timer 1 high byte
TL0
TL0<7>
TL0<6>
TL0<5>
TL0<4>
TL0<3>
TL0<2>
TL0<1>
TL0<0>
00H
TL0<7:0>
Timer 0 low byte
TL1
TL1<7>
TL1<6>
TL1<5>
TL1<4>
TL1<3>
TL1<2>
TL1<1>
TL1<0>
00H
TL1<7:0>
Timer 1 low byte
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
Timer 1
Timer 0
GATE
Gating Control Timer /Counter 1
C/T
Counter (1) or Timer (0) selector
M1,M0
Mode control bits
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 prescaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1
M1,M0 = 11, stopped
GATE
Gating control Timer/Counter 0
C/T
Counter (1) or Timer (0) selector
M1,M0
Mode Control bits
M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 prescaler
M1,M0 = 01, 16 bit time interval or event counter
M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0
M1,M0 = 11, one 8bit time interval or event counter and one 8bit time interval counter
TXT0
X24 POSN
DISPLAY
X24
-
DISABLE
HEADER
ROLL
DISPLAY
STATUS
ROW ONLY
-
VPS ON
INV ON
00H
X24 POSN
0 - Store X/24 in extension memory
1 - Store X/24 in basic page memory with packets 0 to 23
DISLAY X24
0 - Display row 24 from basic page memory
1 - Display row 24 from appropriate location in extension memory
DISABLE
HEADER ROLL
0 - Write rolling headers and time to current display page
1 - Disable writing of rolling headers and time to into memory
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 4 SFR Bit description
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