參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 37/140頁
文件大?。?/td> 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
37
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
PWM P
ULSE
W
IDTH
M
ODULATORS
The device has up to 4 6-bit Pulse Width Modulated (PWM) outputs for analogue control of e.g. volume, balance,
bass, treble, brightness, contrast, hue and saturation. The PWM outputs generate pulse patterns with a
repetition rate of 21.33us, with the high time equal to the PWM SFR value multiplied by 0.33us. The analogue
value is determined by the ratio of the high time to the repetition time, a D.C. voltage proportional to the PWM
setting is obtained by means of an external integration network (low pass filter).
PWM Control
The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control register. The high time
is defined by the value PWxV<5:0>
TPWM T
UNING
P
ULSE
W
IDTH
M
ODULATOR
The device has a single 14-bit PWM that can be used for Voltage Synthesis Tuning. The method of operation
is similar to the normal PWM except the repetition period is 42.66us.
TPWM Control
Two SFR are used to control the TPWM, they are TDACL and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits TD<13:7> alter the high period between o and 42.33us.
The 7 least significant bits TD<6:0> extend certain pulses by a further 0.33us. e.g. if TD<6:0> = 01H then 1 in
128 periods will be extended by 0.33us, if TD<6:0>=02H the 2 in 128 periods will be extended.
The TPWM will not start to output a new value until writing a value to TDACH. Therefore, if the value is to be
changed TACL should be written before TDACH.
SAD S
OFTWARE
A/D
Four successive approximation Analogue to Digital Converters can be implemented in software by making use
of the on board 8-bit Digital to Analogue Converter and Analogue Comparator.
SAD Control
The control of the required analogue input is done using the channel select bits CH<1:0> in the SAD SFR, this
selects the required analogue input to be passed to one of the inputs of the comparator. The second comparator
input is generated by the DAC whose value is set by the bits SAD<7:0> in the SAD and SADB SFR’s. A
comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set, this must be
at least one instruction cycle after the SAD<7:0> value has been set. The result of the comparison is given on
VHI one instruction cycle after the setting of ST
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