參數(shù)資料
型號： TDA935X
廠商： NXP Semiconductors N.V.
英文描述： TV signal processor-Teletext decoder with embedded m-Controller
中文描述： 電視信號處理器與嵌入式米圖文電視解碼器控制器
文件頁數(shù)： 21/140頁
文件大?。?/td> 570K
代理商： TDA935X
Philips Semiconductors
Preliminary specification
1999 Sep 28
21
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
ENSI
0 - Disable I
2
C interface
1 - Enable I
2
C interface
STA
START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes
free. If the device operates in master mode it will generate a repeated START condition.
STO
STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set
in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and
SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware
SI
Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:
-A START condition is generated in master mode.
-The own slave address has been received during AA=1
-The general call address has been received while S1ADR.GC and AA=1
-A data byte has been received or transmitted in master mode (even if arbitration is lost)
-A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or transmitter
While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.
AA
Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions
-Own slave address is received.
-General call address is received(S1ADR.GC=1)
-A data byte is received, while the device is programmed to be a master receiver
-A data byte is received, while the device is selected slave receiver
When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.
S1DAT
DAT<7>
DAT<6>
DAT<5>
DAT<4>
DAT<3>
DAT<2>
DAT<1>
DAT<0>
00H
DAT<7:0>
I
2
C Data
S1STA
STAT<4>
STAT<3>
STAT<2>
STAT<1>
STAT<0>
0
0
0
F8H
STAT<4:0>
I
2
C Interface Status
SAD
VHI
CH<1>
CH<0>
ST
SAD<7>
SAD<6>
SAD<5>
SAD<4>
00H
VHI
0 - Analogue input voltage less than DAC voltage
1 - Analogue input voltage greater then DAC voltage
CH<1:0>
ADC Input channel select
CH<1:0> = 00,ADC3
CH<1:0> = 01,ADC0
CH<1:0> = 10,ADC1
CH<1:0> = 11,ADC2
ST
Initiate voltage comparison between ADC input Channel and SAD<7:0> value
Note: Set by Software and reset by Hardware
SAD<7:4>
Most Significant nibble of DAC input word
SADB
0
0
0
DC COMP
SAD<3>
SAD<2>
SAD<1>
SAD<0>
00H
DC COMP
0 - DC Comparator mode disabled
1 - DC Comparator mode enabled
SAD<3:0>
Least Significant nibble of 8 bit SAD value
SP
SP<7>
SP<6>
SP<5>
SP<4>
SP<3>
SP<2>
SP<1>
SP<0>
07H
SP<7>
Stack Pointer
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TF1
Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
TR1
Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
TF0
Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine
TR0
Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off
IE1
Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.
Names
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
RESET
Table 4 SFR Bit description
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