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參數(shù)資料
| 型號： | TDA935X |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | TV signal processor-Teletext decoder with embedded m-Controller |
| 中文描述： | 電視信號處理器與嵌入式米圖文電視解碼器控制器 |
| 文件頁數(shù)： | 32/140頁 |
| 文件大?。?/td> | 570K |
| 代理商： | TDA935X |
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Philips Semiconductors
Preliminary specification
1999 Sep 28
32
TV signal processor-Teletext decoder with
embedded
μ
-Controller
TDA 935X/6X/8X series
WatchDog Timer
Pulse Width Modulators
To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be disabled prior to
entering Idle to prevent the device being reset. Once in Idle mode, the XTAL oscillator continues to run, but the
internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory Interface,
I2C, Timer/Counters, WatchDog Timer and Pulse Width Modulators are maintained. The CPU state is frozen
along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values.
Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before
entering this mode.
There are three methods available to recover from Idle:-
Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle
mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will
be the one after the instruction that put the device into Idle mode.
A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit. When
Painter is configured in this mode, detection of an analogue threshold at the input to the SAD may be
used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to be executed will be the one following the
instruction that put the device into Idle. For further details of the SAD DC Compare mode refer to the
Software A/D description within the micro-controller section.
The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is
running, the hardware reset need only be active for one machine cycle (12 clocks at 12MHz) to complete
the reset operation. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all
other RAM values. Code execution commences with the Program Counter set to ’0000’.
P
OWER
D
OWN
M
ODE
In Power Down mode the XTAL oscillator is stopped. The contents of all SFR, and RAM is maintained, however
the Auxiliary/Display memory is not maintained. The port pins maintain the values defined by the SFR’s. Since
the output values on RGB and VDS are maintained the teletext/OSD display must be made inoperative before
entering Power Down mode.
The power down mode is activated by setting the PD bit in the PCON register. The WatchDog timer must be
disabled before entering Power down.
There are two methods of exiting power down. Since the clock is stopped, external interrupts needs to be set to
level sensitive, by changing the level of these interrupts the device can be taken out of power down.
The second method of terminating the power down mode is with an external hardware reset. Reset defines all
SFR’s and Display memory, but maintains all other RAM values.
I/O Facility
I/O
PORTS
The device has a number of micro-controller port I/O lines, each are individually addressable.
The I
2
C-bus ports (P1.6 and P1.7) can only be configured as Open-drain.
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