參數(shù)資料
型號(hào)： SYM53C825A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 42/225頁(yè)
文件大?。?/td> 1237K
代理商： SYM53C825A
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2-22
SYM53C825A/825AE Data Manual
Functional Description
Chained Block Moves
Wide SCSI Receive
Bit
T he WSR bit is set whenever the SCSI core is
receiving data (Data In for initiator or Data Out
for target) and the core detects a partial transfer at
the end of a block move or chained block move
SCRIPT S instruction. When WSR is set, the high
order byte of the last SCSI bus transfer is not
transferred to memory. Instead, the byte is tempo-
rarily stored in the SWIDE register. T he hardware
uses the WSR bit to determine what behavior must
occur at the start of the next data receive transfer.
T he bit is automatically cleared at the start of the
next data receive transfer. T he bit can alternatively
be cleared by the microprocessor or through
SCRIPT S. T he bit can also be used by the micro-
processor or SCRIPT S for error detection and
recovery purposes.
SWIDE Register
T his register is used to store data for partial byte
data transfers. For receive data, the SWIDE regis-
ter holds the high-order byte of a partial SCSI
transfer which has not yet been transferred to
memory. T his stored data may be a residue byte
(and therefore ignored) or it may be valid data that
will be transferred to memory at the beginning of
the next Block Move instruction.
SODL Register
For send data, the low-order byte of the SODL
register holds the low-order byte of a partial mem-
ory transfer which has not yet been transferred
across the SCSI bus. T his stored data is usually
“married” with the first byte of the next data send
transfer, and both bytes are sent across the SCSI
bus at the start of the next data send block move
command.
Chained Block Move
SCRIPT S Instruction
A chained Block Move SCRIPT S instruction is
primarily used to transfer consecutive data send or
data receive blocks. Using the chained block move
instruction facilitates partial receive transfers and
allows correct partial send behavior without addi-
tional op code overhead. Behavior of the chained
Block Move instruction varies slightly for sending
and receiving data.
For receive data (Data In for initiator or Data Out
for target), a chained Block Move instruction indi-
cates that if a partial transfer occurred at the end of
the instruction, the WSR flag is set.T he high order
byte of the last SCSI transfer is stored in the
SWIDE register rather than transferred to mem-
ory. T he contents of the SWIDE register should be
the first byte transferred to memory at the start of
the chained block move data stream. Since the
byte count always represents data transfers to/from
memory (as opposed to the SCSI bus), the byte
transferred out of the SWIDE register is one of the
bytes in the byte count. If the WSR bit is clear
when a receive data chained Block Move instruc-
tion is executed, the data transfer occurs similar to
that of the regular block move instruction. Whether
the WSR bit is set or clear, when a normal block
move instruction is executed, the contents of the
SWIDE register will be ignored and the transfer
takes place normally. For “N” consecutive wide
data receive Block Move instructions, the 2nd
through the Nth Block Move instructions should
be chained block moves.
For send data (Data Out for initiator or Data In for
target), a chained Block Move instruction indicates
that if a partial transfer terminates the chained
block move instruction, the last low-order byte
(the partial memory transfer) should be stored in
the lower byte of the SODL register and not sent
across the SCSI bus. Without the chained block
move instruction, the last low-order byte would be
sent across the SCSI bus. T he starting byte count
represents data bytes transferred from memory but
not to the SCSI bus when a partial transfer exists.
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