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參數(shù)資料
| 型號： | SYM53C825A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 26/225頁 |
| 文件大小： | 1237K |
| 代理商： | SYM53C825A |
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2-6
SYM53C825A/825AE Data Manual
Functional Description
Big and Little Endian Support
Big and Little Endian
Support
T he SYM53C825A supports both Big and Little
Endian byte ordering through pin selection. T he
SYM53C825AJ operates in Little Endian mode
only (the BIG_LIT pin is replaced by one of the
JTAG boundary scan signals). In Big Endian
mode, the first byte of an aligned SCSI-to-PCI
transfer will be routed to lane three and succeeding
transfers will be routed to descending lanes. T his
mode of operation also applies to data transfers
over the add-in ROM interface. T he byte of data
accessed at location 0000h from memory is routed
to lane three, and the data at location 0003h is
routed to byte lane 0. In Little Endian mode, the
first byte of an aligned SCSI to PCI transfer will be
routed to lane zero and succeeding transfers will be
routed to ascending lanes. T his mode of operation
also applies to the add-in ROM interface. T he byte
of data accessed at location 0000h from memory is
routed to lane zero, and the data at location 0003h
is routed to byte lane 3.
T he Big_Lit pin gives the SYM53C825A the flexi-
bility of operating with either Big or Little Endian
byte orientation. Internally, in either mode, the
actual byte lanes of the DMA FIFO and registers
are not modified. T he SYM53C825A supports
slave accesses in Big or Little Endian mode.
When a dword is accessed, no repositioning of the
individual bytes is necessary since dwords are
addressed by the address of the least significant
byte. SCRIPT S always uses dwords in 32-bit sys-
tems, so compatibility is maintained between sys-
tems using different byte orientations. When less
than a dword is accessed, individual bytes must be
repositioned. Internally, the SYM53C825A
adjusts the byte control logic of the DMA FIFO
and register decodes to access the appropriate byte
lanes. T he registers will always appear on the same
byte lane, but the address of the register will be
repositioned.
Big/Little Endian mode selection has the most
effect on individual byte access. Internally, the
SYM53C825A adjusts the byte control logic of the
DMA FIFO and register decodes to enable the
appropriate byte lane. T he registers will always
appear on the same byte lane, but the address of
the register will be repositioned.
Data to be transferred between system memory
and the SCSI bus always starts at address zero and
continues through address ‘n’ - there is no byte
ordering in the chip. T he first byte in from the
SCSI bus goes to address 0, the second to address
1, etc. Going out onto the SCSI bus, address zero
is the first byte out on the SCSI bus, address 1 is
the second byte, etc. T he only difference is that in
a Little Endian system, address 0 will be on byte
lane 0, and in Big Endian mode address zero will
be on byte lane 3.
Correct SCRIPT S will be generated if the
SCRIPT S compiler is run on a system that has the
same byte ordering as the target system. Any
SCRIPT S patching in memory must patch the
instruction with the byte ordering that the
SCRIPT S processor expects.
Software drivers for the SYM53C825A should
access registers by their logical name (i.e.,
SCNT L0) rather than by their address. T he logical
name should be equated to the register’s Big
Endian address in Big Endian mode (SCNT L0 =
03h), and its Little Endian address in Little
Endian Mode (SCNT L0 = 00h). T his way, there is
no change to the software when moving from one
mode to the other; only the equate statement set-
ting the operating modes needs to be changed.
Addressing of registers from within a SCRIPT S
instruction is independent of bus mode. Internally,
the SYM53C825A always operates in Little
Endian mode.
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