參數(shù)資料
型號(hào)： SYM53C825A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 21/225頁(yè)
文件大?。?/td> 1237K
代理商： SYM53C825A
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Functional Description
SCSI Core
SYM53C825A/825AE Data Manual
2-1
Chapter 2
Functional Description
T he SYM53C825A is composed of three func-
tional blocks: the SCSI Core, the DMA Core, and
the SCRIPT S Processor. T he SYM53C825A is
fully supported by the SCSI Device Management
System (SDMS), a complete software package that
supports the Symbios product line of SCSI proces-
sors and controllers. T he PCI Bus Power Manage-
ment support (SYM53C825AE) is discussed at
the end of this chapter.
SCSI Core
T he SCSI core supports the 8- or 16-bit data bus.
It supports SCSI synchronous transfer rates up to
20 MB/s, and asynchronous transfer rates up to 10
MB/s on a 16-bit wide SCSI bus. T he SCSI core
can be programmed with SCSI SCRIPT S, making
it easy to “fine tune” the system for specific mass
storage devices or SCSI-3 requirements.
T he SCSI core offers low-level register access or a
high-level control interface. Like first generation
SCSI devices, the SYM53C825A SCSI core can
be accessed as a register-oriented device. T he abil-
ity to sample and/or assert any signal on the SCSI
bus can be used in error recovery and diagnostic
procedures. In support of loopback diagnostics,
the SCSI core may perform a self-selection and
operate as both an initiator and a target.
T he SYM53C825A SCSI core is controlled by the
integrated SCRIPT S processor through a high-
level logical interface. Commands controlling the
SCSI core are fetched out of the main host mem-
ory or local memory. T hese commands instruct the
SCSI core to Select, Reselect, Disconnect, Wait for
a Disconnect, Transfer Information, Change Bus
Phases and, in general, implement all aspects of
the SCSI protocol. T he SCRIPT S processor is a
special high-speed processor optimized for SCSI
protocol.
DMA Core
T he DMA core is a bus master DMA device that
attaches directly to the industry standard PCI Bus.
T he DMA core is tightly coupled to the SCSI core
through the SCRIPT S processor, which supports
uninterrupted scatter/gather memory operations.
T he SYM53C825A supports 32-bit memory and
automatically supports misaligned DMA transfers.
A 536-byte FIFO allows the SYM53C825A to
support 2, 4, 8, 16, 32, 64, or 128 longword bursts
across the PCI bus interface.
SCRIPT S Processor
T he SCSI SCRIPT S processor allows both DMA
and SCSI commands to be fetched from host
memory or internal SCRIPT S RAM. Algorithms
written in SCSI SCRIPT S control the actions of
the SCSI and DMA cores and are executed from
32-bit system RAM. T he SCRIPT S processor exe-
cutes complex SCSI bus sequences independently
of the host
CPU.
T he SCRIPT S processor can begin a SCSI I/O
operation in approximately 500 ns. T his compares
with 2-8 ms required for traditional intelligent host
adapters. Algorithms may be designed to tune
SCSI bus performance, to adjust to new bus device
types (such as scanners, communication gateways,
etc.), or to incorporate changes in the SCSI-2 or
SCSI-3 logical bus definitions without sacrificing
I/O performance. SCSI SCRIPT S are hardware-
independent, so they can be used interchangeably
on any host or CPU system bus.
Internal
SCRIPT S RAM
T he SYM53C825A has 4 K B (1024 x 32 bits) of
internal, general purpose RAM. T he RAM is
designed for SCRIPT S program storage, but is not
limited to this type of information. When the chip
fetches SCRIPT S instructions or Table Indirect
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