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參數(shù)資料
| 型號： | SYM53C825A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個PCI -的SCSI的I / O接口處理器） |
| 文件頁數(shù)： | 126/225頁 |
| 文件大?。?/td> | 1237K |
| 代理商： | SYM53C825A |
SCSI Operating Registers
5-52
SYM53C825A/825AE Data Manual
Bit 1
CSF (Clear SCSI FIFO)
Setting this bit will cause the “full flags” for the
SCSI FIFO to be cleared. T his empties the
FIFO. T his bit is self-resetting. In addition to
the SCSI FIFO pointers, the SIDL, SODL,
and SODR full bits in the SSTAT 0 and
SSTAT 2 are cleared.
Bit 0
ST W (SCSI FIFO Test Write)
Setting this bit places the SCSI core into a test
mode in which the FIFO can easily be read or
written. While this bit is set, writes to the least
significant byte of the SODL register will cause
the entire word contained in this register to be
loaded into the FIFO. Writing the least signifi-
cant byte of the SODL register will cause the
FIFO to load. T hese functions are summarized
in the table below:
Register 50-51 (D0-D1)
SCSI Input Data Latch (SIDL)
Read Only
T his register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the SODL register
and then read back into the SYM53C825A by
reading this register to allow loopback testing.
When receiving SCSI data, the data flows into this
register and out to the host FIFO. T his register dif-
fers from the SBDL register; SIDL contains latched
data and the SBDL always contains exactly what is
currently on the SCSI data bus. T he power-up val-
ue of this register is indeterminate.
Register
Name
Register
Operation
FIFO Bits
FIFO
Function
SODL
SODL0
SODL1
Write
Write
Write
15-0
7-0
15-8
Load
Load
None
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