參數(shù)資料
型號(hào)： SYM53C825A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 25/225頁(yè)
文件大?。?/td> 1237K
代理商： SYM53C825A
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Functional Description
Additional Access to General Purpose Pins
SYM53C825A/825AE Data Manual
2-5
Additional Access to
General Purpose Pins
T he SYM53C825A can access the GPIO0 and
GPIO1 general purpose pins through register bits
in the PCI configuration space, instead of using
the GPCNT L register in the operating register
space to control these pins. In the Symbios SDMS
software, the configuration bits control pins as the
clock and data lines, respectively.
To access the GPIO1-0 pins through the configu-
ration space, connect a 4.7 K
resistor between
the MAD(7) pin and V
SS
. MAD(7) contains an
internal pull-up that is sensed shortly after chip
reset. If the pin is sensed high, GPIO1-0 access is
disabled; if it is low, GPIO1-0 access is enabled.
Additionally, if GPIO1-0 access has been enabled
through the MAD(7) pin and if GPIO0 and/or
GPIO1 are sensed low after chip reset, GPIO1-0
access will be disabled. If GPIO1-0 access through
configuration space is enabled, the GPIO0 and
GPIO1 pins cannot be controlled from the
GPCNT L and GPREG registers, but will be
observable from the GPREG register. When
GPIO1-0 access is enabled, the Serial Interface
Control register at configuration addresses 34-35h
controls the GPIO0 and GPIO1 pins. For more
information on GPIO1-0 access, refer to the Serial
Interface Control register description in Chapter
3. For more information on the GPIO pins, see
Chapter 4. T his does not apply to the
SYM53C825AE.
Note: T he Symbios SDMS software controls the
GPIO0 and GPIO1 pins via the GPCNT L
and GPREG registers. T herefore, if using
SDMS, do not connect a 4.7K
resistor
between MAD(7) and Vss.
JTAG Boundary Scan
Testing
T he SYM53C825AJ includes support for JTAG
boundary scan testing in accordance with the
IEEE 1149.1 specification, with one exception that
is discussed in this section. T he device can accept
all required boundary scan instructions, as well as
the optional CLAMP, HIGHZ, and IDCODE
instructions.
T he SYM53C825AJ uses an 8-bit instruction reg-
ister to support all boundary scan instructions. T he
data registers included in the device are the
Boundary Data register, the IDCODE register,
and the Bypass register. T he device can handle a
10 MHz T CK frequency for T DO and T DI.
Due to design constraints, the RST / pin (System
Reset) will always tri-state the SCSI pins when it is
asserted. T his action cannot be controlled by the
boundary scan logic, and thus is not compliant
with the specification. T here are two solutions that
resolve this issue:
1. Use the RST / pin as a boundary scan
compliance pin. When the pin is deasserted,
the device is boundary scan compliant and
when asserted, the device is non-compliant. To
maintain compliance, the RST / pin must be
driven high.
2. When RST / is asserted during boundary scan
testing, the expected output on the SCSI pins
must be a high-z condition, and not what is
contained in the boundary scan data registers
for the SCSI pin output cells.
Because of package limitations, the
SYM53C825AJ replaces the T EST IN, MAC/
_T EST OUT, BIG_LIT /, and SDIRP1 signals with
the JTAG boundary scan signals.
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