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參數(shù)資料
| 型號(hào)： | SYM53C825A |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| 中文描述： | 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器） |
| 文件頁(yè)數(shù)： | 134/225頁(yè) |
| 文件大?。?/td> | 1237K |
| 代理商： | SYM53C825A |
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Instruction Set of the I/O Processor
Block Move Instructions
6-6
SYM53C825A/825AE Data Manual
Bit 27
Op Code
T his 1-bit field defines the instruction to be
executed as a block move (MOVE).
Target Mode
1. T he SYM53C825A verifies that it is connected
to the SCSI bus as a target before executing
this instruction.
2. T he SYM53C825A asserts the SCSI phase
signals (SMSG/, SC_D/, and SI_O/) as defined
by the Phase Field bits in the instruction.
3. If the instruction is for the command phase,
the SYM53C825A receives the first command
byte and decodes its SCSI Group Code.
a) If the SCSI Group Code is either Group 0,
Group 1, Group 2, or Group 5, and if the
Vendor Unique Enhancement 1 (VUE1)
bit (SCNT L2 bit 1) is clear, then the
SYM53C825A overwrites the DBC
register with the length of the Command
Descriptor Block: 6, 10, or 12 bytes.
b) If the Vendor Unique Enhancement 1
(VUE1) bit (SCNT L2 bit 1) is set, the
SYM53C825A receives the number of
bytes in the byte count regardless of the
group code.
c) If the Vendor Unique Enhancement 1 bit is
clear and group code is vendor unique, the
SYM53C875 receives the number of bytes
in the count.
d) If any other Group Code is received, the
DBC register is not modified and the
SYM53C825A will request the number of
bytes specified in the DBC register. If the
DBC register contains 000000h, an illegal
instruction interrupt is generated.
4. T he SYM53C825A transfers the number of
bytes specified in the DBC register starting at
the address specified in the DNAD register. If
the Op Code bit is set and a data transfer ends
on an odd byte boundary, the SYM53C825A
will store the last byte in the SCSI Wide
Residue Data Register during a receive
operation. T his byte will be combined with the
first byte from the subsequent transfer so that a
wide transfer can be completed.
5. If the SAT N/ signal is asserted by the initiator
or a parity error occurred during the transfer,
the transfer can optionally be halted and an
interrupt generated. T he Disable Halt on
Parity Error or AT N bit in the SCNT L1
register controls whether the SYM53C825A
will halt on these conditions immediately, or
wait until completion of the current Move.
Initiator Mode
1. T he SYM53C825A verifies that it is connected
to the SCSI bus as an initiator before executing
this instruction.
2. T he SYM53C825A waits for an unserviced
phase to occur. An unserviced phase is defined
as any phase (with SREQ/ asserted) for which
the SYM53C825A has not yet transferred data
by responding with a SACK /.
3. T he SYM53C825A compares the SCSI phase
bits in the DCMD register with the latched
SCSI phase lines stored in the SSTAT 1
register. T hese phase lines are latched when
SREQ/ is asserted.
4. If the SCSI phase bits match the value stored
in the SSTAT 1 register, the SYM53C825A
will transfer the number of bytes specified in
the DBC register starting at the address
pointed to by the DNAD register. If the op
code bit is cleared and a data transfer ends on
OPC
Instruction Defined
0
1
MOVE
CHMOV
OPC
Instruction Defined
0
1
CHMOV
MOVE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SYM53C825AE | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
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| SYM53C875 | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| SYM53C875E | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
| SYM53C876E | PCI-Dual Channel SCSI Multi-function Controller(PCI-雙通道SCSI多功能控制器) |
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