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SYM53C825A/53C825AE Data Manual
Introduction
Package and Feature Options
T he SYM53C825A integrates a high-perfor-
mance SCSI core, a PCI bus master DMA core,
and the Symbios SCSI SCRIPT S processor to
meet the flexibility requirements of SCSI-3 and
future SCSI standards. It is designed to implement
multi-threaded I/O algorithms with a minimum of
processor intervention, solving the protocol over-
head problems of previous intelligent and
non-intelligent adapter designs.
T he SYM53C825A is fully supported by the Sym-
bios SCSI Device Management System
(SDMS ), a software package that supports the
Advanced SCSI Protocol Interface (ASPI) and the
ANSI Common Access Method (CAM). SDMS
provides BIOS and driver support for hard disk,
tape, removable media products, and CD-ROM
under the major PC operating systems.
Package and Feature
Options
T he SYM53C825A is packaged in a 160-pin plas-
tic quad flat pack. T he device is also available, as
the SYM53C825AJ, with additional pins that sup-
port JTAG boundary scan testing. T he JTAG
boundary scan signals replace the T EST IN,
MAC/_T EST OUT, BIG_LIT /, and SDIRP1
pins. T he devices that have been upgraded to
include the power management features are:
SYM53C825AE and SYM53C825AJE.
System Engineering Notes
PCI Pad Power Up Sequence
T his power-up sequence should be followed when
separate power supplies are being applied to the
V
DD
-
IO
and V
DD
-
CORE
pins in a chip testing envi-
ronment. Following this recommended power-up
sequence will help prevent potential damage to
these devices.
Description of the Issue
T he Universal PCI pad input receiver in this cell
library has all devices in a common N well
attached to the 5V core V
is powered from the V
DD
DD
PCI supply.
supply. T he P channel
In the event that the I/O V
prior to the core V
between the P channel source and the N well of
the device can become forward biased. T his can
create an excessive current flow between the two
nodes, and it will cause damage to the device.
DD
PCI supply goes high
supply, the parasitic diode
DD
Solution for the Issue
In most system applications and production envi-
ronments, the two V
DD
pins power up simulta-
neously. T he user should know of this potential
hazard if using separate power supplies in a testing
environment.
Either power up the Core and I/O V
taneously, or if this is not possible, power up the
Core V
DD
before powering up the I/O V
supply.
DD
PCI simul-
DD
PCI
Note that a power down situation can have the
same effect. T he I/O must always power down
prior to the Core.