參數(shù)資料
型號(hào)： SYM53C825A
廠商： LSI Corporation
英文描述： PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器)
中文描述： 的PCI -的SCSI I / O處理器（個(gè)PCI -的SCSI的I / O接口處理器）
文件頁(yè)數(shù)： 138/225頁(yè)
文件大?。?/td> 1237K
代理商： SYM53C825A
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Instruction Set of the I/O Processor
I/O Instructions
6-10
SYM53C825A/825AE Data Manual
Initiator Mode
Select Instruction
1. T he SYM53C825A arbitrates for the SCSI bus
by asserting the SCSI ID stored in the SCID
register. If the SYM53C825A loses arbitration,
it tries again during the next available
arbitration cycle without reporting any lost
arbitration status.
2. If the SYM53C825A wins arbitration, it
attempts to select the SCSI device whose ID is
defined in the destination ID field of the
instruction. Once the SYM53C825A has won
arbitration, it fetches the next instruction from
the address pointed to by the DSP register.
T herefore, the scripts can move to the next
instruction before the selection has completed.
It will continue executing SCRIPT S until a
SCRIPT that requires a response from the
target is encountered.
3. If the SYM53C825A is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register. T he SYM53C825A should manually
be set to initiator mode if it is reselected, or to
target mode if it is selected.
4. If the Select with SAT N/ field is set, the
SAT N/ signal is asserted during the selection
phase.
Wait Disconnect Instruction
T he SYM53C825A waits for the target to perform
a “l(fā)egal” disconnect from the SCSI bus. A “l(fā)egal”
disconnect occurs when SBSY/ and SSEL/ are
inactive for a minimum of one Bus Free delay
(400 ns), after the SYM53C825A has received a
Disconnect Message or a Command Complete
Message.
Wait Reselect Instruction
1. If the SYM53C825A is selected before being
reselected, it fetches the next instruction from
the address pointed to by the 32-bit jump
address field stored in the DNAD register. T he
SYM53C825A should be manually set to
target mode when selected.
2. If the SYM53C825A is reselected, it fetches
the next instruction from the address pointed
to by the DSP register.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C825A will abort the Wait
Reselect instruction and fetch the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register.
Set Instruction
When the SACK / or SAT N/ bits are set, the corre-
sponding bits in the SOCL register are set. When
the target bit is set, the corresponding bit in the
SCNT L0 register is also set. When the carry bit is
set, the corresponding bit in the ALU is set.
Clear Instruction
When the SACK /or SAT N/ bits are set, the corre-
sponding bits are cleared in the SOCL register.
When the target bit is set, the corresponding bit in
the SCNT L0 register is cleared. When the carry
bit is set, the corresponding bit in the ALU is
cleared.
Bit 26
Relative Addressing Mode
When this bit is set, the 24-bit signed value in
the DNAD register is used as a relative dis-
placement from the current DSP address. T his
bit should only be used in conjunction with the
Select, Reselect, Wait Select, and Wait Reselect
instructions. T he Select and Reselect instruc-
tions can contain an absolute alternate jump
address or a relative transfer address.
OPC2
OPC1
OPC0
Instruction Defined
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Select
Wait Disconnect
Wait Reselect
Set
Clear
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