參數(shù)資料
型號: SAA6713H
廠商: NXP Semiconductors N.V.
英文描述: XGA dual input flat panel controller
中文描述: 雙輸入的XGA液晶控制器
文件頁數(shù): 89/103頁
文件大?。?/td> 521K
代理商: SAA6713H
2004 Apr 05
89
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
8.1
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in the functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting pin TRST to LOW.
8.2
Device identification codes
A device identification register is specified in “IEEE Std.
1149.1b-1994” It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and determination of the version number of ICs
during field service.
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between pins TDI and TDO of the IC. The
identification register will load a component specific code
duringtheCAPTURE_DATA_REGISTERstateoftheTAP
controller and this code can subsequently be shifted out.
At board level this code can be used to verify component
manufacturer, type and version number. The device
identification register contains 32 bits, numbered 31 to 0,
where bit 31 is the most significant bit (nearest to TDI) and
bit 0 is the least significant bit (nearest to TDO);
see Fig.32.
Table 62
BST instructions supported by the SAA6713H
INSTRUCTION
DESCRIPTION
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO
when no test operation of the component is required.
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the boundary
scan register.
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary scan register is in external test mode.
This optional instruction will provide information on the components manufacturer, part number and
version number.
This optional instruction allows testing of the internal logic (no customer support available).
This private instruction allows testing by the manufacturer (no customer support available).
EXTEST
SAMPLE
CLAMP
IDCODE
INTEST
USER1
handbook, full pagewidth
MHC239
nnnn
0110 0111 0001 0011
0000 0010 101
4-bit
version
code
16-bit part number
11-bit manufacturer
identification
1
31
MSB
LSB
28 27
12
1
0
TDO
11
TDI
Fig.32 32 bits of identification code.
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