參數(shù)資料
型號(hào)： SAA6713H
廠商： NXP Semiconductors N.V.
英文描述： XGA dual input flat panel controller
中文描述： 雙輸入的XGA液晶控制器
文件頁(yè)數(shù)： 46/103頁(yè)
文件大?。?/td> 521K
代理商： SAA6713H
2004 Apr 05
46
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
Table 26
Input interface sync selection; note 1
Note
1.
X = don’t care.
7.5.5
P
IN
VSYNC
CONFIGURATION
Besides serving as input for an external vertical
synchronization pulse VSYNC can be switched as output
of the vsync internally derived from (not shown in Fig.8):
DVI data (VS_DVI)
Sync-on-green slicer (SOG)
Composite sync decoder (VS_CS).
The I/O direction of pin VSYNC is selected by
vsync_out_en of register SYNC_SEL (18H at page 0). In
case of output mode, the source is selected by
sog_out_en and cs_dvi_de of register SYNC_SEL
according to Table 27.
Table 27
Pin VSYNC switching modes; note 1
Note
1.
X = don’t care.
7.6
Interrupt generation
An interrupt signal is provided at output pin INT (active
LOW). The state of INT is based on mode detection,
auto-adjustment, OSD, decoupling FIFO and output
interface interrupt conditions shown in Table 28.
Table 28
Interrupt conditions and description
Interrupt output pin INT is set LOW (active) whenever one
or more of the interrupt flags is HIGH. The interrupt flags
are set HIGH, when the corresponding interrupt condition
is met:
The mode detection interrupt flag is set HIGH when one
of the mode measurement bits toggles or a value
changes significantly at the vsync or in case of vsync or
hsync jitter, depending on which of the conditions are
enabled (see Section 7.11.1).
The auto-adjustment interrupt flag is set HIGH in the
moment an auto-adjustment measurement finishes,
indicating the result values can be read out.
The decoupling FIFO interrupt flag is set HIGH
whenever the decoupling FIFO is full, indicating that the
output timing is too slow and a change of the timing is
required; otherwise a corrupt output picture will occur.
The OSD interrupt flag is set HIGH every time a pointer
animation frame sequence ends to allow to switch the
displayed icon and program the icon for the next turn
(see Section
7.14.3
).
The output interface interrupt flag is set HIGH when the
pixel stream to the output interface is broken, indicating
that the output pixel or line rate is too fast.
The hsync jitter interrupt flag (int_iif) is set HIGH when
line jitter at the analog video input occurs more than a
number of times specified in the register II_HJIT,
indicating that the other clock edge should be used to
sample the hsync and vsync signal.
iif_cs_
sog_en
iif_dvi_
on
iif_hs_
regen_on
HS_IIF
VS_IIF
0
0
1
1
0
1
X
X
X
X
0
1
HSYNC
HS_DVI
HS_CS
HS_REGEN
VSYNC
VS_DVI
VS_CS
vsync_
out_en
sog_
out_en
cs_
dvi_de
DIRECTION
VSYNC
0
1
1
1
X
1
0
0
X
X
1
0
input
output
external
SOG
VS_DVI
VS_CS
INTERRUPT
SUBMODULE
DESCRIPTION
int_mode
mode detection
change of input video
mode detected
int_auto
auto-adjustment auto-adjustment
finished
FIFO overflow
int_fifo
decoupling
FIFO
OSD
int_osd
end of programmed
OSD frame sequence
FIFO underflow
line jitter occurs
(hsync jitter detection)
int_oif
int_iif
output interface
input interface
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