- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385813 > SAA6713H (NXP Semiconductors N.V.) XGA dual input flat panel controller PDF資料下載
參數(shù)資料
| 型號： | SAA6713H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XGA dual input flat panel controller |
| 中文描述： | 雙輸入的XGA液晶控制器 |
| 文件頁數(shù)： | 85/103頁 |
| 文件大小： | 521K |
| 代理商： | SAA6713H |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁當(dāng)前第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁
2004 Apr 05
85
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
7.17.6
T
RANSITION MINIMIZING
The transition minimizing programming is done in the
OI_CTRL0 register in the OIF. This section describes how
the OIF pixel input operates with INVA and INVB outputs
for various values of ivsl0 and ivsl1 (register OI_CTRL0).
All modes are designed for double pixel handling.
7.17.6.1
Bit ivsl0 = 1 and bit ivsl1 = 0
INVA operates with input pixel 0 (means the first of a
couple). This inversion operation considers a total of
18 bits: the 6 high order bits of each colour component of
input pixel 0 (R2 to R7, G2 to G7 and B2 to B7). The input
data of time (n
1) is compared to the data at time n. If
10 or more bits within the 18 bits have changed from LOW
toHIGHorfromHIGHtoLOW,thenINVAtogglesbetween
HIGH and LOW: if INVA was HIGH at (n
1) it goes LOW,
and if it was LOW at (n
1), it toggles HIGH. If 9 or fewer
bits within the 18 bits have changed from HIGH to LOW or
from LOW to HIGH, then INVA does not toggle. When
INVA is HIGH, all bits (24 bits) of pixel 0 to output (means
data before ‘data to output mapping’) are inverted.
INVB operates with input pixel 1 (means the second of a
couple). This inversion operation considers a total of
18 bits: the 6 high order bits of each colour component of
input pixel 1 (R2 to R7, G2 to G7 and B2 to B7). The input
data of time (n
1) is compared to the data at time n. If
10 or more bits within the 18 bits have changed from LOW
toHIGHorfromHIGHtoLOW,thenINVBtogglesbetween
HIGH and LOW: if INVB was HIGH at (n
1), it goes LOW,
and if it was LOW at (n
1), it toggles HIGH. If 9 or fewer
bits within the 18 bits have changed from HIGH to LOW or
from LOW to HIGH, then INVB does not toggle. When
INVB is HIGH, all bits (24 bits) of pixel 1 to output are
output inverted.
7.17.6.2
Bit ivsl0 = 1 and bit ivsl1 = 1
INVA and INVB both operate with input pixel 0 and 1.This
inversion operation considers a total of 36 bits, the 6 high
order bits of each colour component of pixel 0 and 1
(0R2 to 0R7, 0G2 to 0G7, 0B2 to 0B7, 1R2 to 1R7,
1G2 to 1G7 and 1B2 to 1B7). The input data of time
(n
1) is compared to the data at time n. If 19 or more bits
withinthe36 bitshavechangedfromLOWtoHIGHorfrom
HIGH to LOW, then both INVA and INVB toggle between
HIGH and LOW. When INVA and INVB are HIGH at
(n
1), they go LOW, and when they are LOW at (n
1),
theytoggleHIGH.If18 or fewerbitswithinthe36 bitshave
changed from HIGH to LOW or from LOW to HIGH, then
INVA and INVB do not toggle. When INVA and INVB are
both HIGH, all bits (48 bits) are inverted.
Because there is no previous data for the first data in every
column (horizontal period), the above noted toggle
operations for INVA and INVB, as well as the data
inversion operations are not performed. In the event of first
data output of every column, INVA and INVB are set to
LOW, and data is not inverted.
7.17.6.3
Bit ivsl0 = 0 and bit ivsl1 = 0
For input pixel, data inversion is similar to when ivsl0 = 1,
ivsl1 = 0, with input pixel 0 and 1 being separated, and the
outputs being driven according to the results of
calculations.
For INVA and INVB signals, the calculations are similar to
when ivsl0 = 1, ivsl1 = 0, but the INVA and INVB outputs
are driven as logical opposites.
7.17.6.4
Bit ivsl0 = 0 and bit ivsl1 = 1
The INVA and INVB signals are always driven LOW and
data inversion operations are not performed.
7.17.7
B
ACKGROUND AND EMERGENCY FRAME GENERATOR
The output interface includes a simple frame generator.
It may be useful when the front-end receives no signal, so
no front-end clock is available. The generated frame has
thesamedimensionsasthepicturearea.Theframecolour
is programmable (OI_FCx). The on screen display is still
working. The generator may be switched on via the
OI_FC_EN register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7110 | Digital Multistandard Colour Decoder(數(shù)字多標準彩色譯碼器) |
| SAA7111 | Video Input Processor VIP |
| SAA7120H | Digital video encoder |
| SAA7152 | Digital Video Comb Filter DCF |
| SAA7184 | Digital Video Encoders DENC2-M6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
| SAA6721 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
| SAA6721E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。