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參數(shù)資料
| 型號： | SAA6713H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | XGA dual input flat panel controller |
| 中文描述： | 雙輸入的XGA液晶控制器 |
| 文件頁數(shù)： | 86/103頁 |
| 文件大?。?/td> | 521K |
| 代理商： | SAA6713H |
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2004 Apr 05
86
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
7.17.8
G
LOBAL CONTROL
The output interface has four global modes, which can be programmed with bits OI_enable, power_down and
blank_mode (register OI_CTRL0) according to Table 56.
The blank colour is programmable via bits blank_colour_red, blank_colour_green and blank_colour_blue.
Table 56
Global modes; note 1
Note
1.
X = don’t care.
OI_
enable
power_
down
blank_
mode
MODE
ACTION
1
X
0
1
0
1
0
0
1
X
X
0
blank
Power-down
disable
normal
all colours replaced by blank colour values
all registers set to default, like soft reset; all outputs LOW
all outputs reset but incoming data queued to trash
normal operation
7.17.9
P
ANEL CLOCK
The output interface can handle single and double pixel
mode (bit double_pixel in register OI_CTRL1). In single
pixel mode one pixel (24 bits) is available each cycle at the
output ports. The panel clock PCLK is the same as the
back-end clock. In double pixel mode 2 pixels (48 bits) are
available at the output ports. The PCLK in double pixel
mode changes every second cycle of the back-end clock.
The panel clock polarity can be inverted by setting
PCLK_pol of register OI_CTRL1 to logic 1. At the
beginning of each frame the PCLK is synced again. It is
very important that the number of pixels in a double pixel
frame is even.
The horizontal sync signal of the selected video input
sources (DVI or VGA) may be used as a reference clock
for the panel PLL (see Table 57). This allows more stable
locking of the panel timing to the source timing. In this
mode the PLL will be ‘coasted’ during vertical sync when a
composite sync or sync-on-green is enabled
(iif_cs_sog_en = 1).
Table 57
Panel PLL
7.17.10 H
OW TO START THE OUTPUT INTERFACE
Table 58
Starting output interface
pll_src
FUNCTION
0
1
pre-divided clock
HS_PLL (iif_dvi_on = 0) or
HS_DVI (iif_dvi_on = 1)
STEP
ACTION
1
2
3
4
5
set-up frame geometry
set-up signal generators
set-up wait column and wait mode
set-up PCLK and pixel mode
enable output interface
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|---|---|
| SAA6713H/V1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XGA dual input flat panel controller |
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