參數(shù)資料
型號(hào)： SAA6713H
廠商： NXP Semiconductors N.V.
英文描述： XGA dual input flat panel controller
中文描述： 雙輸入的XGA液晶控制器
文件頁數(shù)： 49/103頁
文件大?。?/td> 521K
代理商： SAA6713H
2004 Apr 05
49
Philips Semiconductors
Product specification
XGA dual input flat panel controller
SAA6713H
7.8
DVI interface
The Digital Visual Interface (DVI) provides a high-speed
digital connection for visual data types that is display
technologyindependent.Theinterfaceisprimarilyfocused
at providing a connection between a computer and its
display device.
The DVI uses a communications protocol called Transition
Minimized Differential Signalling (TMDS
)
(1)
. This
protocol uses a digital encoding and decoding algorithm to
minimize the number of transitions (from HIGH-to-LOW or
vice-versa) within a packet of bits, thereby lowering the
energy in the electromagnetic spectrum that the system
radiates. Using TMDS
, it is generally easier to meet
ElectroMagnetic Compatibility (EMC) requirements.
The TMDS
receiver inputs are three data streams of
10-bit frames (TMDS
data) and one clock channel. Per
channel it recovers and decodes these frames into either
8-bit words or two control bits. It also decodes a Data
Enable (DE) signal that indicates when the receiver is
receiving active data and when it is receiving control data.
The clock indicates the frequency of one TMDS
data
packet, i.e. the clock frequency is one tenth of the bit rate.
The DVI interface is automatically enabled when selected
as input source for the input interface.
7.8.1
HDCP
The DVI interface becomes High-bandwidth Digital
Content Protection (HDCP) version 1.0 compliant.
Authentication in hardware is supported. Therefore, the
SAA6713H offers two signals: HSCL and HSDA. They are
the clock and the data signal for the Device Data Channel
(DDC) I
2
C-bus that is used in the authentication
process.The HDCP keys are stored in an on-chip SRAM.
The system microcontroller is supposed to transfer them
from its ROM during initialization phase. No external
EEPROM for key storage is required. The HDCP registers
are mapped in Table 29.
The HDCP related internal configuration registers are
placed on page 1 and the bits are mapped in Table 30.
Moreover, a dedicated software reset for the HDCP circuit
together with the DVI receiver is introduced.
(1) Transition Minimized Differential Signalling (TMDS) is a
subset of PanelLink technology which is a registered
trademark of Silicon Image, Inc.
Table 29
HDCP registers on the Display Data Channel (DDC) I
2
C-bus; notes 1 and 2
REGISTER
ADDRESS
R/W
RESET
FIELDS
DDC_HDCP_BKSV0
DDC_HDCP_BKSV1
DDC_HDCP_BKSV2
DDC_HDCP_BKSV3
DDC_HDCP_BKSV4
Reserved
DDC_HDCP_RI0
DDC_HDCP_RI1
Reserved
DDC_HDCP_AKSV0
DDC_HDCP_AKSV1
DDC_HDCP_AKSV2
DDC_HDCP_AKSV3
DDC_HDCP_AKSV4
Reserved
00H
01H
02H
03H
04H
05H to 07H
08H
09H
0AH to 0FH
10H
11H
12H
13H
14H
15H to 17H
R
R
R
R
R
R
R
W
W
W
W
W
X
X
X
X
X
00H
X
X
00H
X
X
X
X
X
00H
hdcp_bksv[7:0], receiver key selection vector
hdcp_bksv[15:8]
hdcp_bksv[23:16]
hdcp_bksv[31:24]
hdcp_bksv[39:32]
hdcp_ri[7:0], link verification response
hdcp_ri[15:8]
hdcp_aksv[7:0], transmitter key selection vector
hdcp_aksv[15:8]
hdcp_aksv[23:16]
hdcp_aksv[31:24]
hdcp_aksv[39:32]
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